Semiconductor integrated circuit device, semiconductor memory system and clock synchronous circuit

ABSTRACT

A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of application Ser. No. 09/109,181,filed on Jul. 2, 1998, now U.S. Pat. No. 6,222,406, the entiredisclosure of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuitdevice and a semiconductor memory system, and particularly to atechnique effective for use in devices which need minute or micro andhighly-accurately controlled delay signals. This invention also relatesto a clock synchronous circuit having quick response and high accuracyand a technique effective for use in a semiconductor integrated circuitdevice such as a synchronous DRAM (Dynamic Random Access Memory)equipped with the clock synchronous circuit.

The following array oscillator disclosed by ISSCC has been known as anexample of a circuit for obtaining a time resolution of a few 10 psec(picoseconds). This type of array oscillator is known as one wherein thesame ring oscillators are arranged in large numbers in a columndirection and connected in ring form using one inputs with eachindividual stages as two inputs, and the outputs of the respectivestages are respectively supplied to other inputs of adjoining stages,and they are also connected in ring form even in a row direction. Suchan oscillator has been described in ISSCC 93/ANALOG TECHNIQUES/PAPERTA7.5, pp. 118-119, 1993 and ISSCC/SESSION 18/MEMORIES WITH SPECIALARCHITECTURES/PAPER FP18.5, pp308-309, 1995, and Japanese PublishedUnexamined Patent Application No. Hei 8-78951.

A clock synchronous circuit excluding a feedback loop like a synchronousmirror delay (SMD) is characterized in that the time (lock time)necessary for synchronization is short as is the case of 2 to 3 cycles.According to this feature, the lock time can be shortened by measuringthe cycle of an input clock as the number of stages of delay circuits orcoarse delays. The time resolution of this measuring circuit isdetermined depending on a delay time per stage corresponding to acomponent of each delay circuit. The time resolution is normally on theorder of a delay time corresponding to two stages of CMOS invertersJapanese Published Unexamined Patent Application No. Hei 8-237091 isknown as an example of a clock synchronous circuit using such an SMD.

SUMMARY OF THE INVENTION

In order to speed up a semiconductor memory such as a dynamic RAM(Random Access Memory) or the like, memory access times as seen from amemory controller for generally controlling plural RAMs are made uniformby making uniform signal transfer delays on a substrate mounted betweensuch RAMs and the memory controller, in other words, in anticipation ofthe signal propagation delays on the mounted substrate, increasing delaytimes thereinside when such signal delays are small and decreasingdelays thereinside when such signal delays are large, whereby it ispossible to easily ensure the time (window) required to allow datacapturing occupied in a cycle time and speed up a memory cycle time Ifsemiconductor memories are implemented on a mounting substrate havingsignal wires or interconnections whose each characteristic impedance is50Ω, at 1 centimeter (cm) intervals, a signal propagation delay timeencountered between each individual semiconductor memories becomes about50 psec. It is therefore necessary to provide delay circuits each havinga high-precision time resolution of a few 10 psec inside the respectivesemiconductor memories with a view toward making uniform the signaltransfer delays between the memory controller and the respectivesemiconductor memories as described above.

The inventors or the like of the present application have discussed theutilization of the above-described array oscillator to implement thedelay circuits each having the above-mentioned high-precision timeresolution In the array oscillator, however, delay signals having delaysequal to each other by the number of respective stages are to be formedfor the number of logic stages lying in a row direction. However, in acircuit formed on an actually-available semiconductor substrate, eachsignal delay encountered in the row direction will not be recognized tohave satisfactory linearity, and the signal delay will become fast inone logic stage or slow in another logic stage. Thus, it has been foundthat even if the principle of the above-described array oscillator isused as it is, the above-mentioned micro and uniform signal delay like afew 10 psec cannot be obtained.

It has been recognized by the inventors that a problem arises in that ifit is assumed that minute and uniform signal delays are obtained andlogic circuits are disposed on a semiconductor substrate in lattice formalong row and column directions, then signal paths for taking out outputsignals cannot be provided evenly in the cases: where delay signals arerespectively outputted from logic circuits disposed inside the latticeform and where delay signals are respectively outputted from logiccircuits disposed outside the lattice form.

Since the array oscillator is made up of ring oscillators, a start-uptime between its deactivated state and stabilization of its operation isrelatively long. It has been thus evident from the discussions of thepresent inventors that a problem arises in that the formation of adesired signal at high speed falls into difficulties.

A first object of this invention is to provide a semiconductorintegrated circuit device provided with a circuit for forming signalseach having minute and high-accuracy time resolution. A second object ofthis invention is to provide a semiconductor integrated circuit devicehaving a delay circuit disposed on a semiconductor substrate withefficiency and capable of forming delay signals each having micro andhigh-accuracy time resolution. A third object of this invention is toprovide a semiconductor memory system capable of implementing the inputand output of data at high speed.

A fourth object of this invention is to provide a semiconductorintegrated circuit device provided with a circuit for forming signalseach having small and high-accuracy time resolution at high speed.

A summary of a typical one of the inventions disclosed according to thefirst through fourth objects of the inventions of the presentapplication will be described in brief as follows:

There is provided a semiconductor integrated circuit device comprising:

at least one delay circuit including,

M signal lines for receiving a first input signal tosuccessively-delayed M (M=2, 3, 4, . . . )th input signals therein; and

M logic gate circuit groups extending from a first logic gate circuitgroup corresponding to the first input signal to an Mth logic gatecircuit group corresponding to the Mth input signal, and

wherein each individual logic gate circuit groups have N logic gatecircuits extending from a first logic gate circuit to an N (N=3, 4, 5, .. . )th logic gate circuit, each logic gate circuit having a first inputterminal, a second input terminal and an output terminal, couplingelements are provided between the first and second input terminals ofthe logic gate circuits respectively,

the first to Nth logic gate circuits in each logic gate circuit groupare tandem-connected to the output terminals through the first inputterminals respectively,

the M signal lines are connected to the first input terminals of thefirst logic gate circuits in their corresponding logic gate circuitgroups,

first input terminals of L (L=1, 2, 3, . . . )th logic gate circuits ineach of the first logic gate circuit group to M−1th logic gate circuitgroup are connected to second input terminals of Lth logic gate circuitsin the next logic gate circuit group,

first input terminals of predetermined logic gate circuits in the Mthlogic gate circuit group are connected to second input terminals ofpredetermined logic gate circuits in the first logic gate circuit group,and

successively-delayed output signals are respectively obtained from theoutput terminals of a plurality of the Nth logic gate circuits

A summary of another typical one of the inventions disclosed inassociation with the first to fourth objects of the inventions of thepresent application will be described in brief as follows:

There is provided a semiconductor integrated circuit device comprising:

at least one delay circuit including,

a plurality of logic gate circuits which are respectively provided withimpedance elements for respectively coupling two input signals inputtedto first and second input terminals, each impedance element beingprovided between the first and second input terminals, and respectivelyform output signals according to the input signals supplied to the firstand second input terminals,

the plurality of logic gate circuits being capable of being disposed inlattice form in a first signal transfer direction and a second signaltransfer direction, and

wherein the first input terminal of a logic gate circuit KL provided asa Kth other than the first as seen in the first signal transferdirection and disposed in an Lth stage as seen in the second signaltransfer direction is supplied with a signal outputted from a logic gatecircuit provided as the same Kth as seen in the first signal transferdirection and defined as an L−1th stage as seen in the second signaltransfer direction or an input clock signal in the case of thefirst-stage logic gate circuit, and the second input terminal of thelogic gate circuit KL is supplied with an input signal supplied to afirst input terminal of a logic gate circuit provided as the immediatelypreceding K−1th as seen in the first signal transfer direction anddefined as the same Lth stage as seen in the second signal transferdirection;

a second input terminal of a logic gate circuit provided as the first asseen in the first signal transfer direction and defined as an Lth asseen in the second signal transfer direction is supplied with an inputsignal supplied to a first input terminal of a logic gate circuitdefined as the final stage as seen in the first signal transferdirection, the input signal being in phase with an input signal suppliedto a first input terminal of a logic gate circuit at a stage precedingthe final stage as seen in the second signal transfer direction;

the first and second input terminals of the logic gate circuits definedas the first stage as seen in the second signal transfer direction andprovided as the first as seen in the first signal transfer direction arerespectively supplied with a clock signal through a corresponding inputcircuit constituting a buffer, and the input clock signals supplied tothe first input terminals of the respective logic gate circuitsextending from the second to the last as seen in the first signaltransfer direction are delayed in order in the first signal transferdirection by the corresponding input circuit constituting the buffer;and

output signals are respectively obtained from output terminals of aplurality of logic gate circuits placed in at least a plural-numberedstage as seen in the second signal transfer direction and arranged inthe first signal transfer direction.

A summary of a further typical one of the inventions disclosed inassociation with the first to fourth objects of the inventions of thepresent application will be described in brief as follows:

There is provided a semiconductor integrated circuit-device comprising:

a first circuit including a plurality of unit circuits for respectivelyforming a first input clock signal to successively-delayed M (M=2, 3, 4,. . . )th input clock signals in response to a reference clock signal,the first circuit forming the first to Mth input clock signals withinone cycle of the reference clock signal in association with successivelydifferent characteristics of circuit elements respectively included inthe plurality of unit circuits; and

a second circuit for receiving the first to Mth input clock signalstherein and obtaining a plurality of output clock signals successivelydelayed with delay amounts uniform than respective delay amounts of thefirst to Mth input clock signals;

wherein the second circuit is a delay circuit having a plurality oflogic gate circuits corresponding to M rows and N columns (where N=3, 4,. . . ) and wired so that signals are transmitted in row and columndirections of the plurality of logic gate circuits.

A fifth object of this invention is to provide a high-accuracy andquick-response clock synchronous circuit and a semiconductor integratedcircuit device using the clock synchronous circuit. A sixth object ofthis invention is to provide a clock synchronous circuit capable ofimplementing on-standby less power consumption and high-speed reset withhigh accuracy and a semiconductor integrated circuit device using theclock synchronous circuit. A seventh object of this invention is toprovide a clock synchronous circuit capable of realizing fast responsewith high accuracy without an increase in circuit scale and asemiconductor integrated circuit device using the clock synchronouscircuit. Other objects of this invention or the above and other objectsand novel features of this invention will become apparent from thefollowing description of the present specification and the accompanyingdrawings.

A summary of a typical one of the inventions disclosed in correspondencewith the fifth through seventh objects of the inventions of the presentapplication will be described in brief as follows:

A lattice-like delay circuit is configured wherein a first delay circuitor coarse delay for propagating a clock pulse with relatively low timeresolution, a first edge detector and a first multiplexer are used toform or create a clock signal delayed by one clock in association withthe relatively low time resolution, a second coarse delay havingrelatively high time resolution, a second edge detector and a secondmultiplexer are used to correct an error of the first coarse delay,included in the above signal, and a plurality of logic gate means eachof which is provided with impedance means for making coupling betweentwo input signals inputted between first and second input terminals as asecond delay circuit having high time resolution as the above secondcoarse delay and each of which produces an output signal obtained byinverting the input signals, are used so as to be placed in lattice formin first and second signal transfer directions. The lattice-like delaycircuit is used wherein the respective logic gate means extending fromthe first to the last as seen in the first signal transfer direction arerespectively successively supplied with input clock signals with theirdelays as seen in the first signal transfer direction, and outputsignals are obtained from output terminals of the plurality of logicgate means placed in at least the final stage or the immediatelypreceding stage as seen in the second signal transfer direction andarranged in the first signal transfer direction. The lattice-like delaycircuit referred to above is installed in a semiconductor integratedcircuit device such as a synchronous DRAM or the like.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming the subject matter which is regarded as theinvention, it is believed that the invention, the objects and featuresof the invention and further objects, features and advantages thereofwill be better understood from the following description taken inconnection with the accompanying drawings in which:

FIG. 1 is a circuit diagram showing one embodiment of a lattice-likedelay circuit according to the present invention;

FIG. 2 is a circuit diagram illustrating another embodiment of alattice-like delay circuit according to the present invention;

FIGS. 3A and 3B are respectively characteristic diagrams obtained bycomputer simulations, for describing the operation of a lattice-likedelay circuit according to the present invention;

FIGS. 4A, 4B, 4C, 4D and 4E are respectively circuit diagramsillustrating other embodiments of delay elements each employed in alattice-like delay circuit according to the present invention;

FIGS. 5A and 5B are respectively characteristic diagrams for describingthe role of a coupling means employed in a lattice-like delay circuitaccording to the present invention;

FIG. 6 is a characteristic diagram for describing another role of thecoupling means employed in the lattice-like delay circuit according tothe present invention;

FIG. 7 is a waveform diagram for describing the operation of thelattice-like delay circuit according to the present invention;

FIG. 8 is a block diagram showing one embodiment of a clock-generatorusing the lattice-like delay circuit according to the present invention;

FIG. 9 is a circuit diagram illustrating one embodiment of a controlcounter shown in FIG. 8;

FIG. 10 is a circuit diagram depicting one embodiment of a decoder shownin FIG. 8;

FIG. 11 is a circuit diagram showing one embodiment of a multiplexershown in FIG. 8;

FIG. 12 is a circuit diagram illustrating one embodiment of a clockcounter shown in FIG. 8;

FIG. 13 is a block diagram showing another embodiment of the clockgenerator using the lattice-like delay circuit according to the presentinvention;

FIG. 14 is a circuit diagram depicting one embodiment of a delay elementshown in FIG. 13;

FIG. 15 is a block diagram showing one embodiment of a semiconductormemory system to which the present invention is applied;

FIG. 16 is a timing chart for describing the operation of a clockgenerator provided on the DRAM side in the semiconductor memory systemshown in FIG. 15;

FIG. 17 is a block diagram showing one embodiment of a DLL circuit usinga lattice-like delay circuit according to the present invention;

FIG. 18 is a timing chart for describing the operation of the DLLcircuit shown in FIG. 17;

FIG. 19 is a layout diagram illustrating one embodiment of alattice-like delay circuit according to the present invention;

FIG. 20 is an overall block diagram depicting one embodiment of asynchronous DRAM to which the present invention is applied;

FIG. 21 is a block diagram showing one embodiment of a lattice-likeoscillator circuit according to the present invention;

FIG. 22 is a waveform diagram for describing the operation of thelattice-like oscillator circuit according to the present invention;

FIG. 23 is a block diagram showing one embodiment of a clock synchronouscircuit according to the present invention;

FIG. 24 is a timing chart for describing the operation of the clocksynchronous circuit shown in FIG. 23;

FIG. 25 is a circuit diagram illustrating one embodiment of a coarsedelay CD1 shown in FIG. 23;

FIG. 26 is a circuit diagram showing one embodiment of an edge detectorED1 corresponding to the coarse delay CD1 shown in FIG. 23;

FIG. 27 is a circuit diagram illustrating one embodiment of an edgedetector ED2 corresponding to a lattice-like delay circuit SQUAD1 shownin FIG. 23;

FIG. 28 is a circuit diagram depicting one embodiment of a multiplexerMPX2 shown in FIG. 23;

FIG. 29 is a waveform diagram for describing the operation of alattice-like delay circuit employed in the present invention;

FIG. 30 is a timing chart for describing one example of an operation ofa clock synchronous circuit according to the present invention;

FIG. 31 is a timing chart for describing one example of anotheroperation of the clock synchronous circuit according to the presentinvention;

FIG. 32 is a timing chart for describing one example of a furtheroperation of the clock synchronous circuit according to the presentinvention;

FIG. 33 is a timing chart for describing one example of a still furtheroperation of the clock synchronous circuit according to the presentinvention;

FIG. 34 is a timing chart for describing one example of a still furtheroperation of the clock synchronous circuit according to the presentinvention;

FIG. 35 is a timing chart for describing one example of the operation ofthe synchronous SDRAM shown in FIG. 20;

FIG. 36 is a block diagram showing another embodiment of a clocksynchronous circuit according to the present invention; and

FIG. 37 is a block diagram illustrating a further embodiment of a clocksynchronous circuit according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Preferred embodiments of the present invention will hereinafter bedescribed in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing one embodiment of a grid- orlattice-like delay circuit according to the present invention.Respective circuit elements in the same drawing are formed on a singlesemiconductor substrate like monocrystal silicon together with circuitelements constructive of a dynamic RAM or the like requiring the same bythe known semiconductor integrated circuit manufacturing technology.

One of logic gate means used as delay elements arranged in grid orlattice form comprises a NAND gate or NAND gate circuit ND and acoupling capacitor CP provided between two inputs in1 and in2 of theNAND gate ND as typically shown as an illustrative example. Although thecapacitance value of the coupling capacitor CP is not limited inparticular, the coupling capacitor CP is a capacitance element having arelative large capacitance value of about 1 pF as for a semiconductorintegrated circuit.

The logic gate means used as the delay elements are arranged in latticeform so as to take m stages in a Row direction corresponding to a firstsignal transfer direction and n stages in a Column directioncorresponding to a second signal transfer direction. A description willbe made of a first row in the first signal transfer direction. Of thelogic gate means comprised of n stages, which have been arranged in thecolumn direction corresponding to the second signal transfer direction,two input terminals in1 and in2 of the logic gate means corresponding tothe first stage are used in common and supplied with a signal outputtedfrom an inverter INV1 of a buffer. A signal outputted from the firststage is supplied to first and second input terminals in1 and in2 of thesecond stage, which are commonly used in the same manner as describedabove. A signal outputted from the second stage is supplied to a firstinput terminal in1 of the third stage. Signals outputted from thepre-stages are respectively supplied to first input terminals in1 of thefourth to nth stages subsequently in the same manner as described above.

A description will be made of a second row lying in the first signaltransfer direction. Of the logic gate means comprised of n stagesarranged in the column direction corresponding to the second signaltransfer direction, a first input terminal in1 of the logic gate meanscorresponding to a first stage is supplied with a signal outputted froman inverter INV2 of the buffer and a first input terminal in1 of asecond stage is supplied with a signal outputted from the first stage. Asignal outputted from the second stage is supplied to a first inputterminal in1 of a third stage. Subsequently, signals outputted frompre-stages are supplied to first input terminals in1 of a fourth to nthstages respectively. Second input terminals in2 of the respective logicgate means of the first to nth stages are respectively supplied with thesignals to be input to the first input terminals in1 of the respectivelogic gate means of the first stage corresponding to the immediatelypreceding first as seen in the first signal transfer direction to thenth stage.

Even respective mth rows corresponding to a third to a final stages inthe first signal transfer direction are treated in a manner similar tothe above second. Namely, first input terminals in1 of first-stage logicgate means of the logic gate means comprised of n stages arranged in thecolumn direction corresponding to the second signal transfer directionare respectively supplied with signals outputted from inverters INV3through INVm of the buffer. In the mth rows corresponding to the thirdto final stages, a signal outputted from the first stage is supplied toa first input terminal in1 of a second stage and a signal outputted fromthe second stage is supplied to a first input terminal in1 of a thirdstage. Subsequently, signals outputted from pre-stages are respectivelysupplied to first input terminals min of the fourth to nth stages in thesame manner as described above. Second input terminals in2 of therespective logic gate means corresponding to the first to nth stages arerespectively supplied with the signals to be input to the first inputterminals in1 of the respective logic gate means of the first to nthstages corresponding to the immediately preceding second to m−1th asseen in the first signal transfer direction.

Second input terminals in2 of the logic gate means of the third to nthstages, of the n logic gate means set or defined as the first as seen inthe first signal transfer direction and arranged in the second signaltransfer direction are supplied with in-phase input signals of thosesupplied to the first input terminals of the logic gate means of thefirst to nth stages at the mth corresponding to the final stage as seenin the first signal transfer direction. For example, an input signal B1supplied to the first input terminal of the logic gate meanscorresponding to the mth as seen in the first signal transfer directionand defined as the first stage as seen in the second signal transferdirection is defined as an input signal T3 supplied to the second inputterminal in2 of the logic gate means defined as the first as seen in thefirst signal transfer direction and defined as the third stage as seenin the second signal transfer direction. Subsequently, an input signalB2 and an input signal B3 are respectively supplied as an input signalT4 and an input signal T5 in the same manner as described above.

If the nth stage as seen in the second signal transfer direction issupposed to be the final stage, then an input signal Bn−2 lying in thefinal stage m as seen in the first signal transfer direction and lyingin an n−2th as seen in the second signal transfer direction is definedas an input signal Tn supplied to the input terminal in2 of thenth-stage logic gate means corresponding to the first as seen in thefirst signal transfer direction and corresponding to the final stage asseen in the second signal transfer direction.

This will be generally described as follows: The first input terminal ofeach logic gate means (K, L) provided as a Kth other than the first asseen in the first signal transfer direction and disposed in an Lth stageas seen in the second signal transfer direction is supplied with asignal outputted from a logic gate means provided as the same Kth asseen in the first signal transfer direction and defined as an L−1thstage as seen in the second signal transfer direction or an input clocksignal in the case of the first-stage logic gate means. The second inputterminal of the logic gate means (K, L) is supplied with an input signalsupplied to a first input terminal of a logic gate means provided as theimmediately preceding K−1th as seen in the first signal transferdirection and defined as the same Lth stage as seen in the secondtransfer direction.

A second input terminal of a logic gate means provided as the first asseen in the first signal transfer direction and defined as an Lth asseen in the second signal transfer direction is supplied with an inputsignal supplied to a first input terminal of a logic gate means lying inthe final stage as seen in the first signal transfer direction, theinput signal being in phase with an input signal supplied to a firstinput terminal of a logic gate means at a stage preceding the finalstage as seen in the second signal transfer direction.

The first and second input terminals of the logic gate means defined asthe first stage as seen in the second signal transfer direction andprovided as the first as seen in the first signal transfer direction arerespectively supplied with a clock signal through the correspondinginput circuit constituting the buffer. The input clock signals suppliedto the first input terminals of the respective logic gate meansextending from the second to the last as seen in the first signaltransfer direction are delayed in order in the first signal transferdirection by their corresponding input circuits constituting the buffer.

The buffer constitutes an input clock signal delay correcting part. Theinverters INV1 through INVm thereof successively delay their outputsignals. In order to form or produce m clock delayed or delay signals S1through Sm whose phases are shifted by small amounts each other from oneclock input as compared with a clock cycle, for example, inverters INV1through INVm using MOSFETs whose gate widths become an arithmeticprogression, are used. Namely, the input terminals of the inverters INV1through INVm of the buffer are commonly supplied with an output signalof an input circuit IB for receiving a clock signal supplied from anexternal terminal although they are not restricted in particular.However, signals successively delayed in correspondence to the firstsignal transfer direction are created as in the case in which the outputsignal S2 of the inverter INV2 is delayed from the signal S1 outputtedfrom each inverter INV1 and the output signal S3 of the inverter INV3 isfurther delayed. Such signals are defined as clock signals inputted tothe lattice-like delay circuit. The circuits for creating or producingthe successively-delayed signals S1, S2, . . . , Sm are not necessarilylimited to or by the above-described embodiment. Predetermined valuesrequired upon device fabrication, other than the gate widths, can bechanged to modify device characteristics of MOSFETs, for example.Further, circuit elements other than the MOSFETs may be used.

The output signals created by the lattice-like delay circuit are definedas output signals of the logic gate means provided as the nth stagecorresponding to the final stage as seen in the second signal transferdirection and provided as the first to the mth as seen in the firstsignal transfer direction. To obtain output signals being in phase andout of phase with the input clock signal, output signals of the logicgate means lying in an n−1th stage as seen in the second signal transferdirection and provided at the first to the mth as seen in the firstsignal transfer direction are added. If it is desired to selectivelyoutput a plurality of types of delay signals, then plural stages may beselected with those in which minute or small delay intervals areuniform, i.e., the final stage as seen in the second signal transferdirection as the reference, as will be described later.

FIG. 2 is a circuit diagram of another embodiment of a lattice-likedelay circuit according to the present invention. In the presentembodiment, each of logic gate means is provided with an output bufferINVL for taking out or extracting an output signal. The logic gate meansemployed in the present embodiment are similar in other configurationsto those employed in the embodiment shown in FIG. 1. If output buffersare added only to specific stages in the lattice-like delay circuit asseen in the second signal transfer direction, then the specific stagesdiffer from one another in output load conditions. Thus, inputconditions of the specific stages will vary as seen from the followingstage.

Therefore, if only the specific stages in the lattice-like logic gatemeans are set to the different input conditions, then micro delaysignals each having satisfactory precision will not be obtained. In theembodiment illustrated in FIG. 2 to avoid this, all the same outputbuffers INVL are added to the logic gate means placed in lattice form,irrespective of whether the output signals should be taken out from thecorresponding logic gate means. Thus, even if output signals areobtained from logic gate means arranged in a first signal transferdirection at arbitrary stages as seen in the second signal transferdirection, micro signal delay times created thereby will not be placedunder some influences.

The lattice-like delay circuit shown in FIG. 1 or 2 may be understood asone in which some of the aforementioned array oscillator is cut out andutilized in a word. However, the array oscillator will oscillate at itsown most convenient oscillation frequency under boundary conditions inrow and column directions. On the other hand, in the lattice-like delaycircuit according to the invention of the present application, nooscillating operation occurs because there is no feedback loop in acolumn direction corresponding to the second signal transfer direction,and the period or cycle of each output clock signal is identical to thatof an externally input clock signal. Further, although clock signalssuccessively delayed in the first signal transfer direction, which havebeen input to respective delay stages,-are shifted in phase each otherby small amounts as compared with the clock cycle as seen from thebuffer constituting the delay corrector, they are not arranged linearlyon the order of a desired number 10 psec.

However, owing to the connection of the delay corrector with theboundary condition in the first signal transfer direction, i.e., Bn andTn+2, the relationship in phase between the respective delay stages iscorrected as clock delay signals pass through delay elements overseveral stages, whereby the linear phase relationship similar to theabove-described array oscillator is obtained.

Further, since the circuit according to the present embodiment norequires the ring oscillator, the startup time between its deactivatedstate and the stabilization of its operation is relatively short. Thus,the circuit according to the present embodiment is suitable forhigh-speed operation. Owing to the feature that the startup time isshort, the operation of this circuit is stopped when not in use, and asemiconductor chip equipped with the circuit can be reduced in powerconsumption in this condition.

In the embodiment shown in FIG. 2, only the inputs of the logic gatemeans used as other delay elements in the array are electricallyconnected to the logic gate means used as the respective delay elements.Further, the output circuits INVL used so as not to unbalance the phaserelationship realized under the boundary condition in the second signaltransfer direction corresponding to the delay-stage direction due to thedifference in addition are provided. Output signals indicative of thelinear phase relationship (small amounts of delay) are obtained throughsuch output circuits INVL.

FIGS. 3A and 3B respectively show characteristic diagrams obtained bycomputer simulations, for describing the operation of the lattice-likedelay circuit according to the present invention. FIG. 3A illustratesthe propagation of the leading edges at the time that the leading edgesare externally inputted and FIG. 3B depicts the propagation of thetrailing edges at the time that the trailing edges are externallyinputted. In FIGS. 3A and 3B, time bases are taken in their horizontaldirections. Further, the propagation of the leading edges (or thetrailing edges) at the respective logic gate circuit stages arranged inthe row direction is represented by white circles (◯), whereas thepropagation of the trailing edges (or the leading edges) thereat isrepresented by black circles (). The origin of the time base is equalto the leading edge or trailing edge of the external clock input. Theinput clock has a pulse-width duty of 50% and is defined as 200 MHz.

Referring to FIGS. 3A and 3B, the delay signals of the delay correctorbecome predominant in the first and second stages as seen in the secondsignal transfer direction and hence the phase differences therebetweenare not arranged at equal intervals (linearly). It is however understoodthat the small amount of delay becomes constant on the stage sidesubsequent to the fourth stage and the above-described ◯ and  marks arearranged in a straight line. The reason why the edges of respectiveodd-numbered stages differ from each other in position, is that thedelay elements are NAND gate circuits. Since the leading edge is drivenby two parallel-connected P channel MOSFETs and the trailing edge isdriven by two series-connected N channel MOSFETs, input vs. outputtimings differ from each other. On the other hand, since outputsproduced from even-numbered stages are determined according to the sumof the two different output timings, they are placed substantially inthe same positions in both FIGS. 3A and 3B.

FIGS. 4A, 4B, 4C, 4D and 4E respectively show circuit diagrams of otherembodiments of delay elements employed in the above-describedlattice-like delay circuit. In FIG. 4A, a NOR gate or gate circuit NR isused as a delay element. Namely, a capacitor CP used as a coupling meansis provided between two inputs in1 and in2 of the NOR gate NR. A signalAout outputted from the NOR gate NR is coupled to an input terminal ofan NOR gate circuit used as another delay element in an array on the oneside. On the other hand, the signal Aout is coupled to an input terminalof an inverter IVL used as an output buffer for obtaining an outputsignal.

In FIG. 4B, one in which output terminals of two inverters IV1 and IV2are commonly connected to each other, is used as a delay element.Namely, a capacitor CP is electrically connected between input terminalsin1 and in2 of the inverters IV1 and IV2 as a coupling means and outputterminals of the inverters IV1 and IV2 are commonly connected to eachother to thereby obtain an output signal Aout. On the one side, theoutput signal Aout is supplied to an input terminal of a NOR gate usedas another delay element in an array. On the other hand, the outputsignal Aout is supplied to an input terminal of an inverter IVL used asan output buffer for obtaining an output signal.

FIG. 4C shows one in which a resistive element RG is used as a couplingmeans in place of the capacitor while using a NAND gate ND, as a delayelement in the same manner as described above. Other configurations aresimilar to those in the embodiment shown in FIG. 2. Thus, the resistorRG used as the coupling means is applicable even to the circuits shownin FIGS. 4A and 4B. The use of the resistive element allows the couplingelement to be formed in a relatively small form.

FIG. 4D shows, as a delay element, one in which diode-connected MOSFETsM1 and M2 are used as a coupling means in place of the capacitor whileusing a NAND gate ND in the same manner as described above. Namely, thediode-cannected MOSFET M1 transmits or carries a signal current directedfrom input terminals in1 to in2. Reversely, the diode-connected MOSFETM2 feeds a signal current directed from the input terminals in2 to in1.Other configurations are similar to those in the embodiment shown inFIG. 2. The diode-connected MOSFETs M1 and M2 used as the coupling meansin this way can be applied even to the circuits shown in FIGS. 4A and4B. The coupling elements can be formed in the same process as otherMOSFETs by using the MOSFETs M1 and M2.

In FIG. 4E, a differential circuit is used as a delay element. Namely, acoupling capacitor C1 is provided with the gates of parallel-connected Nchannel MOSFETs Q3 and Q4 as positive-phase first input terminals in1+and in2+. P channel MOSFETs Q1 and Q2 are provided at thecommonly-connected drains of the N channel MOSFETs Q3 and Q4 as a loadand an inverted output out− is obtained from the commonly-connecteddrains thereof. With the gates of parallel-connected N channel MOSFETsQ7 and Q8 as antiphase first input terminals in1− and in2−, a couplingcapacitor C2 is provided. P channel MOSFETs Q5 and Q6 are provided atthe commonly-connected drains of the N channel MOSFETs Q7 and Q8 as aload and a positive-phase output out+ is obtained from thecommonly-connected drains thereof. At the sources ofdifferentially-operated MOSFETs Q3 and Q4, and Q7 and Q8, an N channelMOSFET Q9 set so as to allow an operating current to flow is provided.The P channel MOSFETs Q2 and Q6 perform control on a delay time perstage with a current to flow therethrough being controlled by a controlvoltage Vctr1 in a manner similar to the P channel MOSFET Q9.

The coupling capacitors C1 and C2 respectively provided between thegates of the MOSFETs Q3 and Q4 and Q7 and Q8 can be replaced by theresistor or MOS diodes as shown in FIGS. 4C and 4D.

FIGS. 5A and 5B respectively show characteristic diagrams for describingthe role of coupling means employed in the lattice-like delay circuitaccording to the invention of the present application. In the presentembodiment, one in which the outputs of the two inverters are renderedcommon as shown in FIG. 4B, is used as a delay element, andcharacteristic diagrams obtained by computer simulations while using itare illustrated. FIG. 4A shows an example in which a capacitor having arelatively large capacitance value of about 1 pF is used as a couplingmeans as in the embodiment shown in FIG. 2. It is understood thatalthough, with an increase in the degree of coupling between the twoinput signals as described above, delay signals at a delay correctorbecome predominant in the pre-stages like the first and second stages asseen in the second signal transfer direction and phase differencestherebetween are not arranged at equal intervals (linearly), the smallamounts of delay become constant on the stage side subsequent to thefourth stage and the above-described ◯ and  marks are arranged in astraight line.

On the other hand, FIG. 5B shows an example in which the capacitancevalue of the capacitor is reduced so that the degree of coupling betweenthe two input signals is lowered. Decreasing the capacitance value ofthe input coupling capacitor in this way impairs the linearity of theabove-described ◯ and  marks even on the rear stage side as seen in thesecond signal transfer direction. However, the rear stage side isrecognized as has been improved as compared with the pre-stage sideafter all.

FIG. 6 is a characteristic diagram obtained by computer simulationswhere outputs of two inverters are used in common under the sameconditions as FIGS. 5A and 5B and the above coupling capacitor isdeleted. If the coupling means is deleted in this way, then the secondsignal transfer direction is set so as to have a predetermined timedifference on the rear stage side in like manner. It is howeverunderstood that although the delay elements placed substantially overthe first to the third are arranged with small amounts of delaydifferences as seen in the first signal transfer direction in which theyare used as variable delay circuits capable of setting desired smallamounts of delay, no time differences exist from the fourth or later andthey are of no use as the small-amount delay circuits.

It is understood that the tight degree of coupling between the signalssuccessively delayed in the first signal transfer direction and thosesuccessively delayed in the second signal transfer direction in theabove-described manner plays an important role in improving linearity ofsmall amounts of delay obtained by uniformly dividing delay timescorresponding to two stages being in phase as seen in the second signaltransfer direction by the number of delay elements placed in the firstsignal transfer direction. This is because it is considered thatalthough no quantitative circuit analysis is done, two input signalsinterfere with each other and changes in signals at respective delayelements placed in lattice form are averaged, whereby theabove-described small amounts of delay satisfactory in linearity arerealized or implemented. As viewed from another angle, each delayelement referred to above can be regarded as a sort of invertingamplifier. However, when the two input signals are subjected to couplingand thereafter supplied to the input of the inverting amplifier, thetransfer of signals between the respective delay elements placed inlattice form is made uniform as a result of signal amplification at asatisfactory linear portion as seen in its input/output transfercharacteristic, whereby the above-described satisfactory linearity isconsidered to be obtained. Although each coupling element has beenprovided between the two input terminals to make coupling between-thetwo input signals in the present embodiment, the present invention isnot limited to this method. If an effect similar to that obtained by theprovision of the coupling element is obtained by placing two inputinterconnections or wires in close proximity to each other, for example,the present invention does not necessarily require particular provisionof the coupling element.

Since the small amounts of delay are obtained by evenly dividing thedelay times corresponding to the two stages being in phase as seen inthe second signal transfer direction by the number of the delay elementsplaced in the first signal transfer direction, this will not reach aconclusion that the two input signals would be completely coupled toeach other. Namely, this is because such coupling that the signal delayson the signal paths in the two signal transfer directions will impairother signal delay elements each other will lose the meaning of theprovision of the gate circuits or the like in lattice form as the delayelements in the first place.

FIG. 7 is a waveform chart for describing the operation of thelattice-like delay circuit according to the present invention. It isunderstood that if, for example, the leading edges of output signalsshown in the center of a time base are taken as illustrative examples,then the leading edges of the clock signals rise at intervals of about50 psec or the like except for the initial several leading edges. It isunderstood that if the trailing edges of the output signals are takeninto consideration, then the falling edges of clock signals on the rearstage side are placed on the front side of the time base at intervals ofabout 50 psec or the like. It is also understood that the initial clocksignal is dispersedly varies in its falling on the rear side of the timebase.

FIG. 8 is a block diagram showing one embodiment of a clock generatorusing the lattice-like delay circuit according to the present invention.The clock generator according to the present embodiment is installed ona semiconductor memory device such as a dynamic RAM and used to makeuniform signal transfer delays on a substrate mounted between suchplural RAMs and a memory controller for generally controlling the RAMs,in other words, in anticipation of the signal propagation delays on themounted substrate, increase delay times thereinside when such signaldelays are small and decrease delays thereinside when such signal delaysare large to thereby make uniform memory access times as seen from thememory controller.

A grid- or lattice-like delay circuit SQUAD is supplied with a clocksignal CCLK. The lattice-like delay circuit SQUAD generates 64 types ofsmall or micro delay signals in response to the input clock signal CCLKalthough not limited in particular. One of the 64 types of delay signalsformed or produced from the lattice-like delay circuit (SQUAD) isselected by a multiplexer (MPX) and outputted through an output circuitas an output clock signal DCLK. A control counter (CONTROL COUNTER) isan up/down counter for receiving a +1 increment signal INC and a −1decrement signal therein, which forms or produces a 9-bit counted outputand supplies it to a decoder (DECODER).

The decoder (DECODER) forms a select signal comprised of 12 bits so asto control the multiplexer (MPX), and forms a 5-bit preset signal andinputs it to a clock counter (CLK COUNTER). The clock counter (CLKCOUNTER) is activated by a signal READ to count the clock signal CCLK.When a specified clock is input, the clock counter (CLK COUNTER)generates an enable signal (Enable) to activate the output circuit andthereby allows the output circuit to output a clock signal DCLK used asa data strobe delay-controlled by a small amount at its activation.

The unillustrated memory controller outputs a control signal foradjusting or controlling the data strobe signal DCLK to the clockgenerator. The control counter (CONTROL COUNTER) performs a countingoperation such as count-up or count-down in accordance with instructionsissued from the memory controller, associates its counted value withtiming established to output the DCLK and makes fast or slow timingprovided to generate the clock signal DCLK used as the data strobe inunits of about 50 psec. Namely, the count-up or count-down is performedso that immediately after power-on, RAM reading instructions are givenfrom the memory controller under the formation of a training period anda signal read from the RAM matches with desired timing, whereby clocktiming control is carried out.

FIG. 9 is a circuit diagram showing one embodiment of the controlcounter. T-type flip-flops are connected in tandem and supply anon-inverse output Q thereof or an inverse output /Q to an inputterminal T of the following stage circuit through a selection circuitconfigured by combining NOR gates controlled by a decrement signal DECfor providing instructions for a count-down operation and an incrementsignal INC for providing instructions for a count-up operation, therebyallowing the control counter to perform the count-up or count-downoperation.

FIG. 10 is a circuit diagram showing one embodiment of the decoderreferred to above. Of counted outputs CNT0 through CNT9 created by thecontrol counter, the decoder utilizes the counted outputs CNT0 throughCNT5 of the six rightmost bits to form select signals for themultiplexer MPX. Namely, the decoder decodes the low bits CNT0 and CNT1of the counted outputs CNT0 through CNT5 of the six bits to create DEC00through DEC03, decodes the two middle bits CNT2 and CNT3 to form DEC20through DEC23 and decodes-the two leftmost bits CNT4 and CNT5 to createDEC40 through DEC43. These decode signals DEC00 through DEC43represented as 4×3=12 kinds are used as the select signals for themultiplexer MPX.

The counted output CNT6 of the counted outputs CNT6 through CTN8 of thethree leftmost bits, of the counted outputs CNT0 through CNT9 formed bythe control counter is outputted as it is and the counted outputs CNT7and CNT8 of the two leftmost bits thereof are decoded to form DEC70through DEC73. These decode signals DEC6 and DEC70 through 73 aresupplied to the clock counter (CLK COUNTER).

FIG. 11 is a circuit diagram of one embodiment of the multiplexer MPX.The 64 kinds of delay clock signals CLK0 through CLK63 produced by theabove-described lattice-like delay circuit SQUAD are divided into 16pairs or sets with the four as one set as in the case of CLK0 throughCLK3 and thereafter inputted to their corresponding four-inputmultiplexers. As illustratively shown in the same drawing, eachfour-input multiplexer comprises a CMOS switch circuit and an outputCMOS inverter. The four-input multiplexers corresponding to 16 in totalare commonly supplied with the decode outputs DEC00 through DEC03 of thelow bits respectively so that one clock signals are selected from eachindividual multiplexers.

The sixteen clock signals selected from the sixteen multiplexers aredivided into four sets or pairs with the four as one set or pair in thesame manner as described above and thereafter inputted to theircorresponding four-input multiplexers. The four pairs of multiplexersare commonly supplied with the decode outputs DEC20 through DEC23 of themiddle bits so that one clock signals are selected from each individualmultiplexers. The four clock signals selected from the multiplexers areinputted to a four-input multiplexer similar to the above from which oneof the decode outputs DEC40 through DEC43 of the high bits is selectedas an output clock signal CLKOUT.

FIG. 12 is a circuit diagram showing one embodiment of the clock counter(CLK COUNTER). The clock counter is supplied with the output signalsDEC6 and DEC70 through DEC73 of the decoder as counter start values, inother words, initial values. The decode output DEC6 corresponding to theleast significant bit of the five bits is used to control themultiplexer provided in the final counted-output stage.

The clock counter activates the output circuit with a delay of apredetermined clock cycle alone to thereby output a clock signal DCLKfrom the output circuit. Namely, the clock counter shifts a start valueas an initial value in response to a count produced by the controlcounter and delays it by the number of clocks required for its shiftoperation, thereby forming an enable signal ENABLE. Thus, the RAMoutputs data in synchronism with the clock signal DCLK generated withbeing delayed by the specified number of clocks from a reference clock.

In the present embodiment, each multiplexer is provided in such a mannerthat the activation signal (ENABLE) can be created with being delayedonly 0.5 cycle (half cycle) of the clock CCLK. Only one of outputsignals (DEC70 through DEC73) of each decoder is brought to a high levelH and a DCLK generation signal (READ) is inputted to a shift registerusing a master slave flip-flop circuit, followed by generation of theactivation signal DCLK after a predetermined clock cycle. Themultiplexer is realized by controlling a delay signal in the final stageof delay stages based on the four-stage flip-flops corresponding to theoutput signals (DEC70 through D73) by the counted output CNT6 to therebyoutput a master-side output OUTH lying before a half cycle or output anoutput OUT from the slave side of one-cycle delay operation.

When, for example, the external clock of 200 MHz is used as describedabove, the clock counter effects delay control on it in 2.5 nsec unitsand the lattice-like delay circuit SQUAD adjusts or controls thatinterval in about 40 psec units. Therefore, the lattice-like delaycircuit SQUAD generates 64 types of delay signals in steps of 40 psec.This is because 40 psec×64 is equal to 2.5 nsec. Each decoder andmultiplexer employed in the present embodiment are designed based onsuch values. A change range for delay control is 22.5 nsec.

FIG. 13 is a block diagram showing another embodiment of the clockgenerator using the above-described lattice-like delay circuit accordingto the present invention. In the clock generator referred to above,another delay element (COARSE DELAY) is provided in front of thelattice-like delay circuit SQUAD employed in the clock generatordescribed in FIG. 8. The insertion of such a delay element is intendedfor enlargement of a delay control range.

FIG. 14 is a circuit diagram showing one embodiment of the delay element(COARSE DELAY) referred to above. The delay element corresponds to onein which each of delay times of two-input NAND gates and invertersconnected in series serves as a unit for controlling a delay time of anoutput (OUT). Only one of eight control signals outputted from a decoderis brought to a high level so that one NAND gate corresponding to thecontrol signal is gated to supply an input signal IN to one input of theseries-connected NAND gate series or column. Namely, the number ofstages of the series-connected NAND gates and inverters determines thenumber of the control units that the input signal IN transfers based onthe control signals.

Owing to the provision of the delay element (COARSE DELAY) in the stagepreceding the lattice-like delay circuit SQUAD in the embodiment shownin FIG. 13, the lattice-like delay circuit SQUAD may generate eighttypes of delay signals in steps of about 40 psec when, for example, anexternal clock of 200 MHz is used Thus, the lattice-like delay circuitSQUAD and the multiplexer MPX can be greatly reduced in circuit size.

FIG. 15 is a block diagram showing one embodiment of a semiconductormemory system to which the present invention is applied. Thesemiconductor memory system comprises a memory controller MC and aplurality of dynamic RAMs (DRAMs) or memory modules (Modules), whichhave IDs for specifying themselves respectively. A signal SO is used asa signal for setting each ID.

The memory controller MC performs a training operation immediately afterpower-on. Namely, the memory controller MC receives commands (CA0through CA9) in synchronism with a clock signal CCLK to first select thefirst DRAM and causes the first DRAM to output a DCLK together with data(DO0 through DO15). The memory controller MC effects this operation onthe second to eighth DRAMs. In response to these DCLK, the memorycontroller MC controls the above-described clock generator installed inthe respective DRAMs so that they reach a constant delay amount. Thus,when viewed from the memory controller MC, a signal delay on a substrateimplemented or packaged between the memory controller MC and each DRAMis accommodated by the above-described timing control. Thus, data can becaptured by any DRAM in equal timings and a data-capturable timeoccupied in a cycle time can be easily ensured. Therefore, the cycletime can be speeded up and the frequency of the clock signal CCLK can beset to a high frequency of about 200 MHz, for example.

FIG. 16 is a timing chart for describing the operation of each clockgenerator provided on the DRAM side in the semiconductor memory system.In synchronism with an external clock CCLK, each lattice-like delaycircuit SQUAD generates a plurality of clock signals obtained bydelaying it by small amounts. Each multiplexer MPX forms and outputs onedelay signal specified by the above-described counter controller.

A read signal READ is received by the counter controller so that anenable signal Enable is generated with being delayed by the number ofspecified clock signals CCLK. Further, an output signal produced fromthe above-described multiplexer is outputted as an internal clock signalDCLK. In an effective period in which the read signal READ is of an highlevel, a plurality of the clock signals DCLK are outputted. Since theinternal clock signal DCLK is generated to compensate for the delay timeproduced upon transfer of a signal between each DRAM and the memorycontroller in the present embodiment, a memory access using a clocksignal CCLK having a high frequency of 200 MHz, for example is madepossible.

FIG. 17 is a block diagram showing one embodiment of a DLL circuit usinga lattice-like delay circuit according to the present invention. Anexternal clock signal is supplied to the lattice-like delay circuitSQUAD to form or produce a plurality of kinds of delay signals asdescribed above. A multiplexer MPX selects one of the plurality of delaysignals to produce an internal clock signal. A phase comparator (PHASECOMPARATOR) compares the internal clock signal with each clock signalsupplied from the external terminal and supplies the result ofcomparison to a controller (CONTROLLER) from which a control signal isformed. A decoder (DECODER) decodes the control signal to form a selectsignal for the multiplexer MPX, whereby the synchronization of theexternal clock signal with the internal clock signal can be achieved.

Although not limited in particular, the controller comprises a counterand starts counting UP or counting DOWN in response to the output of thephase comparator as indicated by a timing chart shown in FIG. 18. Inorder to shorten the time required to synchronize the external clocksignal with the internal clock signal, the counter, which constitutesthe controller, sets the most significant bit to 1 as an initial valueand allows the multiplexer MPX to output a delay signal from a middlepoint of an adjustment or control range at the lattice-like delaycircuit SQUAD. If the phase of the internal clock signal leads, then thecontroller counts up to increase a delay amount. If the phase of theinternal clock signal lags, then the controller counts down to reduce adelay amount. Owing to such control, the internal clock signalsynchronized in phase with the external clock signal can be formed.Since the delay amount of the lattice-like delay circuit is a few 10psec as described above in the DLL circuit of the present embodiment, aphase lock operation can be implemented with high accuracy.

Even when the delay element shown in FIG. 14 is inserted into the inputside of the lattice-like delay circuit SQUAD and the frequency of theexternal clock signal is low, the lattice-like delay circuit can achievehigh-accuracy phase synchronization. Alternatively, the lattice-likedelay circuit and the multiplexer can be reduced in circuit scale.

FIG. 19 shows a layout of one embodiment of a lattice-like delay circuitaccording to the present invention. Although the lattice-like delaycircuit is illustrated in a circuit-diagram form in the presentembodiment, logic gate means used as delay circuits are drawn inaccordance with a geometric layout of a semiconductor. In the presentembodiment, an nth-stage logic gate means column comprised of m arrangedin the first signal transfer direction and a logic gate means columncorresponding to an n+2th-stage located subsequently by two stages fromthe nth-stage are provided so as to be arranged in line. A logic gatemeans column corresponding to an n+1th stage located later by one stagefrom the nth-stage is disposed so as to be adjacent across the latterhalf and the former half of these two logic gate means columns. Thus,the halves of the logic gate means columns are alternately disposed soas to be shifted from each other, so that the lattice-like delay circuitcan be constructed in the form of the logic gate means arranged in tworows.

In such a layout arrangement, the transfer of signals is performed inlattice form along the first and second signal transfer directions bythe respective logic gate means. In this condition, the lengths of wiresused for their signal transfer can be made equal to each other in therespective logic gate means and the above small amount delays can berealized with high accuracy. Further, even when it is desired to obtaina large number of output signals, the logic gate means column located onthe upper side can obtain output signals from the side above thereof andthe logic gate means column located on the lower side can obtain outputsignals from the side below thereof. Therefore, since signal delays onoutput signal paths can be also made equal to each other,higher-accuracy small amounts of signal delay can be realized.

FIG. 20 is an overall block diagram showing one embodiment of asynchronous DRAM (hereinafter called simply “SDRAM”) to which thepresent invention is applied. Although not restricted in particular, theSDRAM shown in the same drawing is formed on a single semiconductorsubstrate like monocrystal silicon by the known semiconductor ICmanufacturing technique.

The SDRAM has a memory array 200A which constitutes a memory bank 0, anda memory array 200B which constitutes a memory bank 1. The memory arrays200A and 200B are respectively provided with dynamic memory cellsarranged in matrix form. According to the drawing, select terminals ofmemory cells placed in the same column are electrically coupled to wordlines (not shown) every columns and data input/output terminals ofmemory cells placed in the same row are electrically coupled tocomplementary data lines (not shown) every rows.

One of the unillustrated word lines of the memory array 200A is drivento a select level in accordance with the result of decoding of a rowaddress signal by a row decoder 201A. The unillustrated complementarydata lines of the memory array 200A are electrically connected to an I/Oline 202A including sense amplifiers and column selection circuits. Eachof the sense amplifiers in the I/O line 202A including the senseamplifiers and the column selection circuit is an amplifier circuit fordetecting the difference between micro potentials which appear on eachindividual complementary data lines according to the reading of datafrom the memory cells and amplifying it. Each column switch circuit usedtherefor is a switch circuit for individually selecting thecomplementary data lines to make continuity between the complementarydata line and the complementary I/O line. The column switch circuit isselectively operated in accordance with the result of decoding of acolumn address signal by a column decoder 203A.

In a manner similar to the above, a row decoder 201B, an I/O line 202Bincluding sense amplifiers and column selection circuits, and a columndecoder 203B are provided even on the memory array 200B side. The abovecomplementary I/O lines are respectively electrically connected tooutput terminals of write buffers 214A and 214B and input terminals ofmain amplifiers 212A and 212B. Signals outputted from the mainamplifiers 212A and 212B are transmitted to an input terminal of alatch/register 213. A signal outputted from the latch/register 213 isoutputted from an external terminal through an output buffer 211.Further, a write signal inputted from the external terminal istransmitted to the input terminals of the write buffers 214A and 214Bthrough an input buffer 210. The above-described external terminalserves as a data input/output terminal for outputting data D0 throughD15 comprised of 16 bits.

Address signals A0 through A9 supplied from address input terminals arebrought to a column address buffer 205 and a row address buffer 206 inaddress multiplex form. The supplied address signals are held by theircorresponding buffers. In a refresh operation mode, the row addressbuffer 206 captures a refresh address signal outputted from a refreshcounter 208 as a row address signal. The output of the column addressbuffer 205 is supplied to a column address counter 207 as preset datatherefor. The column address counter 207 outputs values obtained bysuccessively incrementing column address signals used as the preset dataor the column address signals to the column decoders 203A and 203B.

A controller 209 indicated by a dotted line in the same drawing issupplied with external control signals such as a clock signal CLK, aclock enable signal CKE, a chip select signal /CS, a column addressstrobe signal /CAS (symbol / means that a signal provided with / is arow enable signal), a row address strobe signal /RAS and a write enablesignal /WE, etc., and control data inputted from the address inputterminals A0 through A9 and forms or produces internal timing signalsfor controlling operation modes of the SDRAM and the operations of thecircuit blocks, based on changes in the levels of these signals, timingand the like Further, the controller 209 includes a mode register 10, acommand decoder 20, a timing generator 30, a clock buffer 40 and asynchronous clock generator 50.

The clock signal CLK is inputted to the synchronous clock generatorthrough the clock buffer 40 where an internal clock is generated. Theclock generator using the lattice-like delay circuit is used as for thesynchronous clock generator. The internal clock is used as a timingsignal int.CLK for activating the output buffer 211. A clock signal,which has passed through the clock buffer, is transmitted to othercircuits as it is. If a delay between the internal clock and theexternal clock presents a problem, then the synchronized clock signalmay be formed, followed by supply even to the timing generator 30.

Other external input signals are rendered significant in synchronismwith the leading edge of the internal clock signal. The chip selectsignal /CS provides instructions for starting a command input cycle,based on its low level. The transition of the chip select signal /CS toa high level (chip non-selected state) and other inputs do not makesense. However, the state of selection of each memory bank and theinternal operations such as a burst operation, etc. to be describedlater are not affected by the transition of the signal to the chipnon-selected state. The respective signals of /RAS, /CAS and /WE differin function from corresponding signals employed in the normal DRAM butserve as significant signals when a command cycle to be described lateris defined.

The clock enable signal CKE is a signal for providing instructions forvalidity of the following clock signal. If the clock enable signal CKEis of a high level, then the leading edge of the next clock signal ismade effective. If the clock enable signal CKE is low in level, then theleading edge thereof is made ineffective. When an external controlsignal /OE for performing the control of output enable on the outputbuffer 211 in an read mode is provided although not shown in thedrawing, such a signal /OE is also supplied to the controller 209. Whenthe external control signal /OE is high in level, for example, theoutput buffer 211 is brought to a high output impedance state.

The row address signals are respectively defined by A0 to A8 levels in arow address strobe/bank active command cycle to be described latersynchronized with the leading edge of the clock signal CLK (internalclock signal).

The address signal A9 is regarded as a bank select signal in the rowaddress strobe/bank active command cycle. Namely, when the input of A9is low in level, the memory bank 0 is selected, whereas when it is highin level, the memory bank 1 is selected. Although not restricted inparticular, the control on the selection of the memory bank can beperformed by processes such as the activation of only the row decoder onthe selected memory bank side, all the non-selection of the columnswitch circuits on the non-selected memory bank side, connections to theinput buffer 210 and the output buffer 211 on the selected memory bankside alone, etc.

The address signal A8 in a precharge command cycle to be described laterindicates the aspect of a precharge operation made to complementary datalines or the like. A high level thereof indicates that objects to beprecharged are both memory banks. A low level thereof indicates that onememory bank specified by the address signal A9 is an object to beprecharged.

The above-described column address signals are defined by A0 through A7levels in a read or write command (corresponding to a columnaddress/read command or a column address/write command) cyclesynchronized with the leading edge of the clock signal CLK (internalclock). Each column address defined in this way is set as a startaddress for burst access.

Principal operation modes of the SDRAM, which are to be instructed bycommands, will now be described.

(1) Mode Register Set Command (Mo)

This is a command for setting the mode register 10, which is specifiedby /CS, /RAS, /CAS and /WE=low level. Data (register set data) to be setis given through each of A0 through A9. Although not restricted inparticular, the register set data may be defined as a burst length, aCAS latency, a write mode, etc. Although not restricted in particular,the settable burst length may be defined as 1, 2, 4, 8 and a full page,the settable CAS latency may be defined as 1, 2 and 3, and the settablewrite mode may be defined as burst write and single write.

The CAS latency indicates what cycles of internal clock signal arewasted from the falling edge of the /CAS to the output operation of theoutput buffer 211 upon a read operation specified by a columnaddress/read command to be described later. An internal operation timefor the reading of data is required until the read data is establishedor determined. Therefore, the CAS latency is used to set the internaloperation time according to the use frequency of the internal clocksignal. In other words, when an internal clock signal having a highfrequency is used, the CAS latency is set to a relatively large value.On the other hand, when an internal clock signal having a low frequencyis used, the CAS latency is set to a relatively small value. When thereis provided such a CAS latency function, the function of the clockcounter in the clock generator shown in FIG. 8 or 13 is omitted.

(2) Row Address Strobe/bank Active Command (Ac)

This is a command for providing instructions for a row address strobeand making the selection of each memory bank effective. This command isspecified by /CS and /RAS low level and /CAS and /WE high level. At thistime, addresses supplied to A0 through A8 are captured as row addresssignals, and a signal supplied to A9 is captured as a select signal foreach memory bank. Their capturing operations are performed insynchronism with the leading edge of the internal clock signal asmentioned above. When the corresponding command is specified, forexample, a word line in a memory bank specified by the command isselected. Thus, memory cells connected to the corresponding word lineand their corresponding complementary data lines are brought intoconduction.

(3) Column Address/read Command (Re)

This is a command required to start a burst read operation. Further, itis also a command for providing instructions for a column addressstrobe. This command is specified according to /CS and /CAS=low leveland /RAS and /WE=high level. At this time, column addresses supplied toA0 through A7 are captured as column address signals respectively. Thus,the captured column address signals are supplied to the column addresscounter 207 as burst start addresses. Prior to the burst read operationspecified thereby, a memory bank and a word line lying therein have beenselected in the row address strobe/bank active command cycle. Upon theburst read operation in this condition, the memory cells connected tothe selected word line are successively selected in accordance with eachaddress signal outputted from the column address counter 207 insynchronism with the internal clock signal and their items of data aresequentially read therefrom. The number of the sequentially-read data isset as a number specified by the above-described burst length. Theoutput buffer 211 starts reading data while waiting for the number ofcycles in the internal clock signal defined by the CAS latency.

(4) Column Address/write Command (Wr)

When the burst write is set to the mode register 10 as a write operationmode, this command is defined as a command required to start thecorresponding burst write operation. When the single write is set to themode register 10 as a write operation mode, this command is defined as acommand required to start the corresponding signal write operation.Further, the corresponding command provides instructions for columnaddress strobes at the signal write and the burst write. The command isspecified by /CS, /CAS and /WE=low level and /RAS=high level. At thistime, the addresses supplied to A0 through A7 are captured as columnaddress signals respectively. Thus, the captured column address signalsare supplied to the column address counter 207 as burst start addressesupon the burst write. A procedure for the burst write operationspecified thereby is also performed in a manner similar to the burstread operation. However, no CAS latency is provided for the writeoperation and the capturing of the write data is started from the columnaddress/write command cycle.

(5) Precharge Command (Pr)

This is defined as a command for starting a precharge operation to beeffected on a memory bank selected by A8 and A9. This command isspecified by /CS, /RAS and /WE=low level and /CAS=high level.

(6) Autorefresh Command

This is a command required to start aurorefresh and specified by /CS,/RAS and /CAS=low level and /WE and CKE=high level.

(7) Burst Stop/in/full Page Command

This is a command required to stop all the memory banks from a burstoperation for a full page. This command is ignored in burst operationsother than that for the full page. This command is specified by /CS and/WE=low level and /RAS and /CAS=high level.

(8) No-operation Command (Nop)

This is a command for indicating the non-execution of a substantialoperation, which is specified by /CS=low level and /RAS, /CAS and/WE=high level.

When another memory bank is specified in the course of a burst operationand the row address strobe/bank active command is supplied while theburst operation is being performed in one memory bank in the SDPAM, noinfluence is imposed on the operation at one memory bank under thecorresponding execution and the operation of a row address system inanother memory bank is enabled. For example, the SDRAM has means forholding therein data, addresses and control signals supplied from theoutside. Although not restricted in particular, the held contentsthereof, particularly, the addresses and control signals are held everymemory banks. Alternatively, data corresponding to one word line in thememory block selected according to the row address strobe/bank activecommand cycle is to be held in the latch/register 213 for purposes ofthe read operation in advance before the column-system operation.

Thus, while a non-processed command is being executed, the prechargecommand and the row address strobe/bank active command for a memory bankdifferent from the memory banks to be processed by the command beingunder execution are issued unless data D0 through D15 comprised of 16bits collide with each other at a data input/output terminal to therebymake it possible to start an internal operation in advance.

Since the SDRAM is capable of inputting and outputting data, addressesand control signals in synchronism with the clock signal CLK (internalclock signal), a large-capacity memory similar to a DRAM can beactivated at high speed equivalent to that for a SRAM. It can beunderstood that how many data should be accessed to the selected oneword line, is specified by a burst length, whereby a plurality of piecesof data can be read or written continuously while selected states in acolumn system are being successively switched by the built-in columnaddress counter 207.

When the clock generator is provided as in the present embodiment, thetime intervals between issuing a read command from the memory controllerand restoring data thereto can be set equal to each other among all theSDRAMs. Thus, the frequency of the clock signal CLK can be made highlike 200 MHz. The SDRAM may be set to a system for outputting data insynchronism with the leading edge and trailing edge of the clock signalintCLK.

FIG. 21 is a circuit diagram showing one embodiment of a lattice-likeoscillation circuit to which the present invention is applied. Thepresent embodiment is partially similar in circuit configuration itselfto one disclosed by the above-described reference or literature exceptfor the delay circuits arranged in lattice form. However, the logic gatemeans used as the delay circuits arranged in lattice form are equivalentto ones in which the coupling means are respectively provided betweenthe two inputs as shown in FIGS. 1, 2 and 4 in order to obtainoscillation signals made different in phase from each other with smallamounts of delay equal to each other.

FIG. 22 illustrates an operational waveform chart at the time that theoutputs of the two CMOS inverters used as each individual delay circuitsreferred to above are used in common and a coupling capacitor similar tothe above is added between two inputs thereof. This operational waveformchart is drawn by computer simulations in the same manner as describedabove. The manner in which oscillating operations are performed withequal small amounts of delay is understood from the drawing. Even in thecase of the present lattice-like oscillation circuit, small amounts ofdelay in mutual oscillation signals can be equalized to each other andthe output thereof can be easily taken out by adopting the layoutillustrated in the embodiment of FIG. 19 for at least some of thecircuit.

Operations and effects obtained from the above-described embodiments areas follows:

(1) An advantageous effect is obtained in that a plurality of logic gatemeans each of which is provided with impedance means for coupling twoinput signals inputted between first and second input terminals and eachof which forms an output signal obtained by inverting the input signals,are used so as to be disposed in lattice form in first and second signaltransfer directions, the first input terminal of a logic gate means KLprovided as a Kth other than the first as seen in the first signaltransfer direction and disposed in an Lth stage as seen in the secondsignal transfer direction is supplied with a signal outputted from alogic gate means provided as the same Kth as seen in the first signaltransfer direction and defined as an L−1th stage as seen in the secondsignal transfer direction or with an input clock signal in the case ofthe first-stage logic gate means, the second input terminal of the logicgate means KL is supplied with an input signal supplied to a first inputterminal of a logic gate means provided as the immediately precedingK−1th as seen in the first signal transfer direction and defined as thesame Lth stage as seen in the second signal transfer direction, and asecond input terminal of a logic gate means provided as the first asseen in the first signal transfer direction and defined as an Lth asseen in the second signal transfer direction is supplied with an inputsignal supplied to a first input terminal of a logic gate means lying inthe final stage as seen in the first signal transfer direction, theinput signal being in phase with an input signal supplied to a firstinput terminal of a logic gate means at a stage preceding the finalstage as seen in the second signal transfer direction, the first andsecond input terminals of the logic gate means defined as the firststage as seen in the second signal transfer direction and provided asthe first as seen in the first signal transfer direction arerespectively supplied with a clock signal through the correspondinginput circuit constituting a buffer, the input clock signals supplied tothe first input terminals of the respective logic gate means extendingfrom the second to the last as seen in the first signal transferdirection are delayed in order in the first signal transfer direction bythe corresponding buffer, whereby output signals having small amounts ofdelay can be obtained from output terminals of a plurality of logic gatemeans placed in at least the final stage or the immediately precedingstage as seen in the second signal transfer direction and arranged inthe first signal transfer direction.

(2) Another advantageous effect can be obtained in that satisfactorysignal coupling can be carried out with relative ease by providingcapacitive elements as the impedance means.

(3) A further advantageous effect can be obtained in that satisfactorysignal coupling can be done with relative ease by using resistiveelements as the impedance means.

(4) A still further advantageous effect can be obtained in that alattice-shaped delay circuit can be configured with relative ease byusing NANG gates as the logic gate means.

(5) A still further advantageous effect can be obtained in that alattice-like delay circuit can be configured with relative ease by usingNOR gates as the logic gate means.

(6) A still further advantageous effect can be obtained in that alattice-like delay circuit can be configured easily by using, as thelogic gate means, ones in which output terminals of two inverters arecommonly connected to each other.

(7) A still further advantageous effect can be obtained in that an inputsignal supplied to a first input terminal of a logic gate means placedin the final stage as seen in a first signal transfer direction anddisposed in a first stage as seen in a second signal transfer directionis supplied to its corresponding second input terminal of a logic gatemeans placed in the first as seen in the first signal transfer directionand placed in a third stage as seen in the second signal transferdirection, and first and second input terminals of a logic gate meansplaced in the first as seen in the first signal transfer direction andplaced in a second stage as seen in the second signal transfer directionare commonly supplied with a signal outputted from the first logic gatemeans extending in the first and second signal transfer directions, sothat the shortest time as seen in the second signal transfer directioncan be equally delayed by the number of stages extending in the firstsignal transfer direction, thereby making it possible to achieve smallamounts of delay with efficiency.

(8) A still further advantageous effect can be obtained in that thelattice-like delay circuit is formed on a semiconductor substrate bylaying out Nth logic gate means and N+2th logic gate means placed in thefirst signal transfer direction side by side so as to extend in the samedirection and laying out N+1th logic gate means across the latter halfof the Nth and the former half of the N+2th so as to be adjacentthereto, whereby the lengths of wires for interconnecting the logic gatemeans with each other can be made equal to each other and small amountsof signal delay can be achieved with high accuracy, and output signalscan be easily taken out from the logic gate means.

(9) A still further advantageous effect can be obtained in that since alattice-like oscillation circuit comprises a plurality of logic gatemeans each of which is provided with impedance means for coupling twoinput signals inputted between first and second input terminals to eachother and forms an output signal obtained by inverting the input signalssupplied to the input terminals, it can obtain oscillation signalsshifted by small amounts of delay equal to each other.

(10) A still further advantageous effect can be obtained in that sincethe lattice-like oscillation circuit is formed on a semiconductorsubstrate by laying out Nth logic gate means and N+2th logic gate meansplaced in the first signal transfer direction so as to extend in thesame direction and laying out N+1th logic gate means across the latterhalf of the Nth and the former half of the N+2th so as to be adjacentthereto, whereby the lengths of wires for interconnecting the logic gatemeans with each other can be made equal to each other and oscillatingoperations with small amounts of signal delay with high accuracy can beachieved, and output signals can be easily taken out from the logic gatemeans.

(11) A still further advantageous effect can be obtained in that eachmultiplexer selects one of signals outputted from the lattice-like delaycircuit, a phase comparator compares a clock signal inputted to thelattice-like delay circuit and a clock signal outputted through themultiplexer, a control circuit supplied with the phase-compared outputsignal forms a control signal for the multiplexer to thereby allow theclock signal outputted through the multiplexer to be synchronized withthe input clock signal with high accuracy.

(12) A still further advantageous effect can be obtained in that anup-down counter is used as the control circuit and allowed to perform a+1 or −1 counting operation in response to the output of the phasecomparator, and the result of counting thereof is decoded to form acontrol signal so as to control the corresponding multiplexer, wherebythe high-accuracy DLL circuit can be easily implemented.

(13) A still further advantageous effect can be obtained in that in asemiconductor memory comprising: a memory array in which memory cellsare arranged in matrix form at points of intersection of a plurality ofword lines and a plurality of bit lines; an address selectioncircuit-for selecting a corresponding memory cell in such a memory arrayand a synchronous clock generator for receiving control signals and aclock signal therein and generating an internal clock signalcorresponding to the clock signal in accordance with the controlsignals; and an input/output circuit for outputting a read signal fromthe memory cell in synchronism with the internal clock signal generatedfrom the synchronous clock generator, the lattice-like delay circuit isused as the synchronous clock generator to thereby allow a data outputoperation with high accuracy.

(14) A still further advantageous effect can be obtained in that the useof a counter as the control circuit makes it possible to select one of aplurality of output signals of the lattice-like delay circuit after thenumber of clocks specified with respect to the input clock signal hasbeen counted.

(15) A still further advantageous effect can be brought about in that asemiconductor memory system can be obtained wherein a semiconductormemory device for forming an internal clock signal using thelattice-like delay circuit and outputting the read signal from thememory cell is provided in plural form, one memory control circuit isprovided for the plurality of semiconductor memory devices, and suppliesread/write control signals and the clock signal to each individualsemiconductor memory devices and generates a control signal for mutuallyequalizing delay times for the transfer of signals to the respectivesemiconductor memory devices to thereby form control signals for thelattice-like delay circuits provided in the semiconductor memorydevices, whereby data can be read out at high speed.

(16) A still further advantageous effect can be brought about in that asemiconductor memory system can be obtained wherein a memory module forforming an internal clock signal using the lattice-like delay circuitand outputting the read signal from the memory cell is provided inplural form, one memory control circuit is provided for the plurality ofmemory modules, and supplies read/write control signals and the clocksignal to each individual semiconductor memory devices and generates acontrol signal for mutually equalizing delay times for the transfer ofsignals to the respective semiconductor memory devices to thereby formcontrol signals for the lattice-like delay circuits provided in therespective semiconductor memory devices, whereby data can be read out athigh speed.

The invention of the present application is not necessarily limited tothe aforementioned embodiments. It is needless to say that variouschanges can be made thereto within the scope not departing from itssubstance. For example, a specific configuration of RAM can be widelyapplied to such a semiconductor memory such as a general-purpose DRAM, adynamic RAM having an input/output function based on Rambusspecifications, a static RAM or the like, that data is inputted andoutputted in accordance with a clock signal supplied from theabove-described external terminal and to a memory system using thesemiconductor memory. It can be also widely applied to varioussemiconductor integrated circuit devices each of which forms an internalclock signal synchronized with a clock signal supplied from the outsideand needs to delay its phase by a small amount with respect to theexternal clock signal.

A layout of a lattice-like delay circuit or a lattice-like oscillationcircuit may be one wherein a circuit is formed on a semiconductorsubstrate in a lattice state. The lattice-like delay circuit isavailable similarly even when internally-generated timing signals areoutputted while being delayed by small amounts. The lattice-likeoscillation circuit can be widely used in a semiconductor integratedcircuit device for forming a plurality of kinds of oscillation signalsdifferent in phase from each other.

FIG. 23 is a block diagram showing one embodiment of a clock synchronouscircuit according to the present invention. Respective circuit blocksshown in the same drawing are formed on a single semiconductor substratelike monocrystal silicon together with unillustrated other circuits bythe known semiconductor manufacturing technique.

In the present embodiment, two types of delay circuits are used toensure a synchronizable frequency band, scale down a circuit size andreduce synchronous errors. One delay circuit comprises such delaycircuits (Coarse Delays) CD1 through CD3 that times in respective stagesare long like 300 psec or more, i.e., delay circuits low in timeresolution's accuracy to ensure the synchronizable frequency band. Thesecoarse delays CD1 through CD3 are constructed by tandem connections ofCMOS inverters identical in circuit configuration to each other.

The other delay circuit make use of such lattice-like delay circuitsSQUAD1 through SQUAD2 that times in respective stages according to thedevelopment by the inventors or the like of the present application arelow like 20 to 100 psec. The combination of two kinds of ones large andsmall in time resolution makes it possible to ensure the synchronizablefrequency band, scale down the circuit size and reduce the synchronouserrors. Namely, a configuration is adopted wherein rough synchronizingsignals are formed or produced by the coarse delays CD1 through CD3relatively low in time resolution and synchronous errors includedtherein are corrected by the lattice-like delay circuits SQUAD1 andSQUAD2 low in time resolution.

In the present embodiment, the three CD1 through CD3 are used as thecoarse delays low in time resolution to form the synchronized clocksignal with high accuracy. One coarse delay CD1 delays an input clockpulse CDMin and supplies it to an edge detector (Edge Detector) ED1. Theedge detector ED1 compares each of edges of delay signals in respectivestages of the coarse delay CD1 and an edge of a clock pulse inputtedwith a delay of one clock. If both edges coincide with each other on atime basis, then the edge detector ED1 detects the position (i.e., thenumber of stages N of passed delay element circuits) of the edge at thecoarse delay CD1.

A multiplexer MPX1 and a multiplexer MPX2 are controlled based on adetected signal CNTLA produced from the edge detector ED1 so that outputpulses CDMout and CDout are respectively outputted from the coarsedelays CD2 and CD3 identical in configuration to the coarse delay CD1.The output pulse CDMout outputted from the multiplexer MPX1 is suppliedto the lattice-like delay circuit SQUAD1 which supplies its delay signalto an edge detector ED2. The edge detector ED2 compares each of edges ofdelay signals in respective stage of the lattice-like delay circuitSQUAD1 with an edge of a clock pulse inputted with a further delay ofone clock If both edges coincide with each other, then the edge detectorED2 detects the position (i.e., the number of stages N of passed delayelement circuits) of the edge at the lattice-like delay circuit SQUAD1.

A multiplexer MPX3 is controlled by a detected signal CNTLB producedfrom the edge detector ED2 so that an output pulse Fdout is outputtedfrom the delay circuit SQUAD2 identical in configuration to thelattice-like delay circuit SQUAD1. The FDout is supplied to anunillustrated other circuit as an internal clock signal CLKoutsynchronized through an output driver DRV2.

The internal clock signal CLKout is one synchronized with an input clocksignal CLKin supplied from an external terminal. The input clock signalCLKin is supplied to a common node COMMON of the synchronous circuitthrough a receiver RCV1 used as an input buffer and a driver DRV1, whereit is used as the above-described input clock pulse. Namely, the inputpulse captured by the common node COMMON to which the output of thedriver DRV1 is electrically connected, is delayed through dummy delaycircuits DMDL1 and DMDL2 without being supplied to the input of thecoarse delay CD1 as it is, thereby setting it as the signal CDMin to beinputted to the coarse delay CD1. The dummy delay circuit DMDL2 performstiming so that the lattice-like delay circuits SQUAD1 and SQUAD2 high intime resolution can demonstrate their desired performance. The dummydelay circuit DMDL1 forms or produces delay times corresponding to delaytimes of the receiver RCV1, driver DRVl and multiplexer MPX3.

FIG. 24 is a timing chart for describing the operation of the clocksynchronous circuit. The clock signal CLKin inputted from the externalterminal is delayed by a delay time d1 through the receiver RCV1 and thedriver DRV1, so that the clock pulse at the common node COMMON varies.The input pulse captured by the common node COMMON is delayed by a delaytime dDM1 through the dummy delay circuit DMDL1 and thereafter delayedby a delay time dMD2 through the dummy delay circuit DMDL2. As a result,the so-delayed input pulse is set as the input pulse CDMin for thecoarse delay CD1.

The input pulse CDMin propagates through the coarse delay CD1. Theleading edge thereof is compared with the leading edge of a pulseinputted to the common node COMMON with a delay of one cycle. An Nthstage corresponding to the position of an edge of a pulse delayed by adelay time tDA in the coarse delay CD1 is detected so that its detectedsignal CNTLA is formed.

The multiplexers MPX1 and MPX2 are controlled by the detected signalCNTLA so that delay signals CDMout and CDout in the same Nth stage areoutputted through the coarse delays CD2 and CD3. They are supplied totheir corresponding different lattice-like delay circuits SQUAD1 andSQUAD2. In the same manner as described above, the leading edge of aclock propagated through the lattice-like delay circuit SQUAD1 iscompared with that of a pulse inputted to the common node COMMON with adelayed of two cycles. Thus, an Mth stage corresponding to the edge of apulse delayed by a delay time tDB in the lattice-like delay circuitSQUAD1 is detected so that a detected signal CNTLB thereof is produced.Namely, since the input of the lattice-like delay circuit SQUAD1 issupplied with an output pulse CDin of the dummy delay circuit DMDL1,which is delayed by a delay time tDA in the coarse delay CD2 and furtherdelayed by a delay time dMPXA in the multiplexer MPX1, the edge of apulse delayed by the delay time tDB corresponding to the differencetherebetween is selected.

The multiplexer MPX3 is controlled by the detected signal CNTLB tooutput an Mth-stage delay signal FDout corresponding to the delay timetDB of the lattice-like delay circuit SQUAD2 having the same circuitconfiguration as the lattice-like delay circuit SQUAD1. An output clockpulse CLKout delayed by a delay time d2 through the output driver DRV2is synchronized with the above-described input clock pulse CLKin withina small error range corresponding to high time resolution of thelattice-like delay circuit SQUAD1 in a third cycle.

A quantitative description of the above operation is as follows: Sincethe difference in time between the edge propagated through the coarsedelay CD1 and the edge at the common node COMMON becomes one clockcycle, the following formula (1) is established for the edge comparisonat the coarse delay CD1 low in time resolution.

dMD 1+dMD 2+tDA=tCK−δA  (1)

where tDA indicates the time required to propagate a clock edge througheach of the coarse delays CD1 through CD3, tCK indicates a clock cycle,and δA indicates an error produced or encountered between timeresolutions of the coarse delays CD1 through CD3.

The following formula (2) is established similarly even for the edgecomparison at the lattice-like delay circuit SQUAD1 high in timeresolution.

dDM 1+tDA+dMPXA+tDB=tCK−δB  (2)

where dDM1 indicates a delay time of the dummy delay circuit DMDL1,dMPXA indicates a delay time of the multiplexer MPX1, and δB indicatesan error produced between time resolutions of the lattice-like delaycircuits SQUAD1 and SQUAD2. δB is smaller than δA and on the order of 10psec.

A propagation time τ between the input clock signal CLKin and the outputclock signal CLKout can be represented as the following formula (3) byfinding the sum of delay times in order of the propagation path.

τ=d 1+tDA+dMPXA+tDB+dMPXB+d 2  (3)

If the above expression (3) is rewritten using the above formula (2),then it can be represented as the following formula (4):

τ=d 1+tCK−δB−dDM 1+dMPXB+d 2  (4)

If the delay time dDM1 of the dummy delay circuit DMDL1 is set so as tobe equal to the sum (d1+d2+dMPXB) of the time delay d1 of the receiverRVC1 used as the input buffer and the driver DRV1, the time delay d2 ofthe output buffer DRV2 and the delay time dMPXB of the multiplexer MPX3from the formula (4), then the following expression (5) is established.CLKin and CLKout are synchronized with each other with the error δB.

τ=tCK−δB  (5)

The dummy delay circuit DMDL2 is a delay circuit for adjusting orcorrecting errors produced in the lattice-like delay circuits SQUAD1 andSQUAD2. Arranging tDB in accordance with the above expressions (1) and(2) yields the following formula (6):

 tDB=dDM 2−dMPXA+δA−δB  (6)

If the delay time dDM2 of the dummy delay circuit DMDL2 is made longfrom the formula (6), then the delay time tDB produced in thelattice-like delay circuits SQUAD1 and SQUAD2 can be increased. Sincethe lattice-like delay circuits SQUAD1 and SQUAD2 are unstable inoperation and have damped vibrating variations in delay time at thedelay stages on the initial-stage side as will be described later, thedelay time dDM2 of the dummy delay circuit DMDL2 is used for timeadjustments or timing for using an operating or active region capable ofobtaining a high-accuracy small delay time stabler while avoiding theuse of the delay output on the initial-stage side referred to above.

The maximum cycle tCKmax of a clock signal synchronizable by the clocksynchronous circuit of the present-embodiment is determined according tothe maximum delay time of the coarse delays CD1 through CD3, in otherwords, the length of a CMOS inverter column. If the maximum value of thecoarse delays CD1 through CD3, i.e., the entire propagation delay timeis regarded as tDAmax, then the following formula (7) is establishedfrom the expression (1).

tCK<dDM 1+dDM 2+tDAmax=tCKmax  (7)

On the other hand, restrictions imposed on the minimum cycle of thesynchronizable clock can be eliminated. As the clock cycle becomesshort, dDM1+dDM2>tCK is established, so that a positive delay time tDAwhich satisfies the formula (1), does not exist. However, if thefollowing formula (8) is established, then synchronization is madepossible as indicated by the following expressions (9) through (12).

dDM 1+dDM 2+tDA=ntCK−δA(n=1, 2, . . . )  (8)

The following formula is obtained from the above expression (8):

(dDM 1+dDM 2)/tCK<n<(tDAmax+dDM 1+dDM 2)/tCK  (9)

Therefore, if the following formula is established,

tDAmax>dDM 1+dDM 2  (10)

the formula (9) is rewritten as follows:

(dDM 1+dDM 2)/tCK<n<2(dDM 1+dDM 2)/tCK  (11)

Thus, tCK below dDM1+dDM2 is as follows:

2(dDM 1+dDM 2)/tCK−(dDM 1+dDM 2)/tCK=(dDM 1+dDM 2)/tCK>1  (12)

Therefore, a natural number n, which satisfies the formula (11), alwaysexists.

Thus, if tDmax is set so as to meet the expression (10), it is thenpossible to eliminate the restrictions on the minimum cycle of thesynchronizable clock. However, the number of clock cycles required togenerate the synchronizing clock increases with an increase in n.Namely, although three clock cycles were required for synchronizationeven at the lowest because of measurements of two clock cycles in total:one cycle in the case of the coarse delay CD1 and one cycle in the caseof the lattice-like delay circuit SQUAD1, the number of clock cyclesincreases to the two clock cycles or more. In order to limit the numberof the clock cycles low in reverse, it is necessary that a delay d11 ofthe internal clock driver DRV1 and a delay d10 of the clock receiverRCV1 are reduced so that the delay times dDM1 and dDM2 of the dummydelay circuits DMDL1 and DMDL2 are diminished.

FIG. 25 is a circuit diagram showing one embodiment of the coarse delayCD1. The coarse delay CD1 is constructed in such a manner that four CMOSinverters are tandem-connected in the form of 16 stages as a singledelay element CDunit. The coarse delay CD1 is provided so as to obtaindelay signals CD00 through CD15 from the respective stages. Namely, thecoarse delay CD1 is made up of 4×16=64 CMOS inverters. The other coarsedelays CD2 and CD3 are also made up of the same inverters respectively.A delay signal having a relatively low time resolution of about 300 psecis formed by making up the delay element CDunit of the four CMOSinverters.

FIG. 26 is a circuit diagram showing one embodiment of an edge detectioncircuit or edge detector ED1. FIG. 27 is a circuit diagram illustratingone embodiment of an edge detector ED2 corresponding to the lattice-likedelay circuit SQUAD1. As indicated by a specific circuit of a unitcircuit in FIG. 27, it comprises two through latch circuits connected intandem. Namely, each through latch circuit on the input side comprises aCMOS inverter N1, a CMOS switch comprised of an N channel MOSFETQ1 and aP channel MOSFET Q2, a CMOS inverter N3 that constitutes a latchcircuit, and a feedback clocked inverter CN1 Each through latch circuiton the output side comprises a CMOS switch comprised of an N channelMOSFET Q3 and a P channel MOSFET Q4, a CMOS inverter N4 that constitutesa latch circuit, and a feedback clocked inverter CN2. An inverter N2 forcomplementarily controlling the CMOS switches is provided and suppliedwith a clock signal through a NAND gate G1.

One input of the edge detector ED2 is supplied with delay signals CDijat respective stages of the lattice-like delay circuit SQUAD1 The otherinput thereof is supplied with a clock pulse inputted to a common nodeCOMMON through the NAND gate G1. A propagation delay signal of eachstage on the leading edge of the clock pulse inputted to the common nodeCOMMON is captured. Thereafter, the captured output QB and an output Qcorresponding to a delay stage lying one stage behind are compared by aNOR gate. Levels different from each other between both signals, i.e., alow-leveled output QB of ones each brought to a high level and alow-leveled output Q of ones which have not yet been brought to the highlevel, are detected and outputted on the leading edge of the clock pulseof the common node COMMON.

Since the synchronizable clock frequency band is widened as describedabove in the edge detector ED1 corresponding to the coarse delay CD1shown in FIG. 26, a two-input NOR gate A, an inverter B and a two-inputNAND gate C are added to each edge detector. They serve as a circuit fortaking out an edge detected signal closest to an input CDMin of thecoarse delay CD1 because a plurality of leading edges existsimultaneously in the coarse delay CD1 as the cycle of the clock CLKinbecomes short. When an edge is detected, the corresponding NOR gate Aforms an output signal low in level to deactivate the two-input NORgates A and NAND gates C subsequent thereto so that their gates areclosed through the inverter B. The NOR gates and inverters are used topropagate this non-operating signal. It is necessary to set a delay timethereat so as to be smaller than delay times of delay elements inrespective stages of the coarse delay CD1. Thus, the delay elements ofthe coarse delay CD1 are made up of four CMOS inverters so as to servefor circuit simplification and are set to the relatively low timeresolution as described above.

Each edge detector referred to above is inputted with the clock CLKthrough the NAND gate G1. When the common node COMMON is set to a fixedlevel or an enable signal ENABLE is taken low in level, the supply ofthe input pulse to the common node COMMON can be stopped Thus, the edgedetector stops the above-described edge detecting operation and hencethe detected signal prior to its stop is outputted through the latchcircuit on the output side. Such clock control and output latch functionare utilized for a low power consuming operation to be described later.

FIG. 28 is a circuit diagram showing one embodiment of a multiplexerMPX3. In the present embodiment, a lattice-like delay circuit SQUAD2forms or produces 50 delay signals like CD00 through CD49 but selects 36delay signals of these without having to use unstable pre-stagecircuits. The multiplexers are connected in three stage in tree form soas to select one from delay outputs at 36 stages. Namely, themultiplexers MPX-R corresponding to the first and output stages arerespectively configured as three-input circuits and multiplexers MPX-Deach corresponding to a second stage are respectively configured asfour-input circuits. Thus, the twelve three-input multiplexers MPX-D areprovided. Delay signals CDij and edge detected signals Eij comprised ofCD00/E00 through CD35/ED35 (not shown) are put into 12 pieces three bythree and thereafter inputted to the multiplexers. Further, twelveoutput signals and enable signals are inputted to three four-inputmultiplexers MPX-D in parts respectively. Thereafter, three outputs andenable signals are outputted from their corresponding multiplexers MPX-Dand one of them is outputted from the multiplexer MPX-R corresponding tothe output stage.

Although CD00/E00˜are illustrated as the input terminals of themultiplexer MPX3 in the same drawing, it should be noted that the delaystages CD00 through CD49 of the lattice-like delay circuit SQUAD1 andthe edge detected outputs E00 through E49 do not coincide with oneanother.

FIG. 29 is a waveform diagram for describing the operation of eachlattice-like delay circuit employed in the present invention. It isunderstood from the drawing that if, for example, the leading edge of anoutput signal given in the center of a time base is taken as anillustrative example, then the leading edges of clock signals rise atequal intervals of about 50 psec except for the initial several riselines. It is understood that in regard to the trailing edges of theoutput signals, the falling edges f the output signals on the rear-stageside exist on the front side of the time base at equal intervals ofabout 50 psec, whereas on the rear side of the time base, the trailingedges of the initial clock signals varies.

The dummy delay circuit DMDL2 is provided so as not to use delay signalscorresponding to the initial several lines on the front side of the timebase. A synchronous error δB can be reduced by using the above-describedareas varied at equal intervals of about 50 psec.

Since the above-described lattice-like delay circuits SQUAD1 and SQUAD2can obtain high time resolution by activating the NAND gates asso-called linear circuits as described above, they supply a relativelarge current to be used up as distinct from the normal CMOS circuit.However, since the clock cycle is measured once every plural cycles ofthe input clock pulse CLKin, the clock synchronous circuit can greatlyreduce an operating current.

The edge detector shown in FIG. 27 holds the immediately preceding edgedetected signal therein. Thus, even if a clock cycle measuring blockcomprised of dummy delay circuits DMDL1 and DMDL2, coarse circuits ordelays CD1 and CD2, edge detectors ED1 and ED2, a multiplexer MPX1 and alattice-like delay circuit SQUAD1 stops operating by taking an enablesignal ENABLE low in level as indicated by a timing chart shown in FIG.30, and an input signal CDin of the coarse delay CD1, an input signalCDMin of the coarse delay CD2 and an output signal CDMout of themultiplexer MPX1 are set to a fixed state indicative of a low level,CDout can be produced by a coarse delay CD3 and a multiplexer MPX2,FDout can be formed by a lattice-like delay circuit SQUAD2 and amultiplexer MPX3 and an internal clock signal CLKout can be createdthrough an output-stage driver DRV2, based on the result of measurementsof clock cycles immediately before its stop.

Referring to FIG. 23, the enable signal ENABLE is formed by a timerTimer provided within a chip as in the case of selfrefresh of the knowndynamic RAM. The enable signal ENABLE is brought to a high level in theproportions of once to plural cycles of a clock signal CLKin by thetimer Timer to thereby activate the clock cycle measuring blockcomprised of the above-described dummy delay circuits DMDL1 and DMDL2,coarse delays CD1 and CD2, edge detectors ED2 and ED2, multiplexer MPX1and lattice-like delay circuit SQUAD1 so that an edge detected signal isupdated every time it is activated. Since the three clocks are necessaryfor the clock cycle measurement, it is necessary to bring the enablesignal ENABLE to the high level during three cycles of the clock signalCLKin.

The cycle of the timer Timer is set so that a synchronous error δBproduced due to a change in temperature of the chip or the like fallswithin an allowable range (100 psec or less). The cycle thereof can beset to more than or equal to about 100 msec. Owing to the intermittentoperation of the clock cycle measuring block, power consumption can beprevented from increasing while the synchronous error δB is beingmaintained with high accuracy by using the above-described lattice-likedelay circuit SQUAD large in power consumption.

As described above, the clock synchronous circuit according to thepresent embodiment needs three clock cycles even at the minimum forclock synchronization. However, when no synchronous information existpreviously as is the case at power-on and synchronous information priorto the stop of the clock cycle measuring block exists and is effective,an internal clock signal CLKout synchronized in each clock cycle can beobtained.

FIG. 31 is a timing chart for describing one example of anotheroperation of the clock synchronous circuit according to the presentinvention. The same drawing shows an example of a restart operation of aclock cycle measuring block by a timer Timer. When a timing signal TMoutis outputted from the timer Timer, an enable signal Enable is changedfrom a low level to a high level according to the trailing edge at acommon node COMMON without immediately generating the enable signalEnable. As a result, a constant time margin can be ensured until thecommon node COMMON changes from the low to high levels.

When the enable signal Enable is taken high in level, the clock cyclemeasuring block comprised of the above-described dummy delay circuitsDMDL1 and DMDL2, coarse delays CD1 and CD2, edge detectors ED1 and ED2,multiplexer MPX1 and lattice-like delay circuit SQUAD1 is activated todelay the leading edges transitioned to the high level of the commonnode COMMON respectively. As a result, signals CDin, CDMin and CDMoutare brought to high levels respectively so that a synchronous operationis performed by the edge detectors ED1 and ED2.

FIG. 32 is a timing chart for describing one example of a furtheroperation of the clock synchronous circuit according to the presentinvention. The same drawing shows an example of the operation oftransition to a power-down mode. When a clock enable signal CKE is takenlow in level in the power-down mode, a driver DRV1 stops operating tothereby fix a common node COMMON corresponding to the output to a lowlevel. Thus, a clock cycle measuring block comprised of theabove-described dummy delay circuits DMDL1 and DMDL2, coarse delays CD1and CD2, edge detectors ED1 and ED2, multiplexer MPX1 and lattice-likedelay circuit SQUAD1, the output of the coarse delay CD3 and the outputof the lattice-like delay circuit SQUAD2 for forming an internal clocksignal CLKout are also fixed to a low level in association with the lowlevel at the common node COMMON, respectively, whereby no substantialoperation is performed. Namely, since the coarse delay CD3 and thelattice-like delay circuit SQUAD2 are made up of CMOS circuitsrespectively, they can stop the supply of an operating current accordingto the fixing of the common node COMMON corresponding to the input tothe low level.

FIG. 33 is a timing chart for describing one example of a still furtheroperation of the clock synchronous circuit according to the presentinvention. The same drawing shows an example of a reset operationthereof from the power-down mode. Resetting of the clock synchronouscircuit from the power-down mode is instructed by a high level of theclock enable signal CKE. Owing to the high level of the signal CKE, aninternal signal ICKE is taken high in level to start the operation of adriver DRV1 An input clock signal CLKin supplied from an externalterminal is inputted through the receiver RCV1. With the start of theoperation of the driver DRV1, an output CLK0 produced from the receiverRCV1 is transmitted to the common node COMMON.

Since a multiplexer MPX2 selects one delay stage of a coarse delay CD3according to a pre-stop detected signal held in a latch circuit of theedge detector ED1 supplied with the signal transmitted to the commonnode COMMON, an output signal CDout of the multiplexer MPX2 is deliveredto the input of a lattice-like delay circuit SQUAD2 and the output ofthe lattice-like delay circuit SQUAD2 is outputted through a multiplexerMPX3 according to a pre-stop detected signal held in a latch circuit ofthe edge detector ED2. Thus, an internal clock signal CLKout can beformed with a delay of one cycle.

FIG. 34 is a timing chart for describing one example of a still furtheroperation of the clock synchronous circuit according to the presentinvention. The same drawing shows an example of a clock synchronizingoperation thereof in the power-down mode. When a timer Timer forms anoutput signal TMout in the power-down mode in which the clock enablesignal CKE is brought to a low level, the above-described internalsignal ICKE is raised to a high level correspondingly. Thus, a driverDRV1 starts operating to change the common node COMMON in the samemanner as described above in response to a clock signal CLKin suppliedfrom an external terminal.

Along with this, the timer Timer changes an enable signal Enable to ahigh level in response to a change of the common node COMMON to a lowlevel. Accordingly, an internal clock signal CLKout is generated with adelay of one cycle in the same manner as described above. Further, aclock cycle measuring block comprised of the above-described dummy delaycircuits DMDL1 and DMDL2, coarse delays CD1 and CD2, edge detectors ED1and ED2, multiplexer MPX1 and lattice-like delay circuit SQUAD1 startsoperating in response to the high level of the enable signal Enable soas to spend or expend three cycles, followed by replacement of the edgedetected signals held in the edge detectors ED1 and ED2 with newsignals.

Thus, since synchronization between the clock signal CLKin periodicallysupplied from the external terminal and the internal clock signal CLKoutis effected by the timer Timer even if the power-down mode in which theclock enable signal CKE is brought to the low level, is kept on over arelatively long time, an internal clock signal CLKout synchronized witha clock signal CLKin supplied from the external terminal after one cyclecan be obtained upon resetting of the clock synchronous circuit from thepower-down mode as shown in FIG. 33.

FIG. 35 is a waveform chart for describing a DDR of an SDRAM. In thesame drawing, a waveform chart corresponding to double data rate (DDR)specifications is illustrated In the DDR specifications, an internaltiming signal int.Com-CLK synchronized with a clock signal Ext.CLKsupplied from an external terminal is formed or produced and thereafterdelayed to thereby form or create an internal timing signal int.Data-CLKadvanced by a predetermined time from the next clock. In this condition,data D0 through D3 or the like are outputted in timing at which theinternal timing signal int.Data-CLK. rises and falls. Namely, the outputsignals D0 through D3 or the like are outputted in accordance with therising and falling of the clock signal int.Data-CLK. Since the data canbe outputted twice during one cycle of the clock signal in thisconfiguration, a high-speed output operation can be implemented. Sinceread data are outputted in accordance with the internal timing signalint.Data-CLK preceding the external clock Ext.CLK, an unillustratedmicroprocessor or the like can capture the data D0 through D3 read fromthe SDRAM using the leading edges of the external clock Ext.CLK and itsinverted external clock Ext.CLKB.

In the DDR specifications, a time margin is reduced with an increase inthe frequency of the clock signal CLK since the data are outputted everyhalf cycles of the clock signal CLK. Thus, high-accuracy synchronizationis enabled by using the clock synchronous circuit according to thepresent embodiment. Using the above-described clock synchronous circuitlow in time resolution becomes an essential condition for the SDRAMusing a high-frequency clock signal CLK and set to the DDRspecifications.

The application of the clock synchronous circuit according to thepresent invention to the dynamic RAM, i.e., a memory for transferringdata on a protocol base, such as a Rambus or a sync Link for inputtingand outputting data in synchronism with a clock signal similarly inaddition to ones set to synchronous specifications, is advantageous inhigh accuracy and fast response or the like. Further, a reduction inpower consumption can be also allowed by providing a command used tomake a shift to the intermittent measurement of clock cycles by thetimer Timer and activating the clock cycle measuring block until theabove command is inputted upon power-on.

FIG. 36 is a block diagram showing another embodiment of a clocksynchronous circuit according to the present invention. In the presentembodiment, a switch is provided on the input side of a lattice-likedelay circuit SQUAD so as to perform switching between a signaltransmitted through a dummy delay circuit DMDL and a signal transmittedthrough an input buffer (receiver) Rec, thereby inputting either one ofthe signals to the lattice-like delay circuit SQUAD. A plurality ofswitches S provided at delay outputs of respective stages of thelattice-like delay circuits SQUAD correspond to each edge detectorreferred to above. Further, circuits provided at their lower partscorrespond to the multiplexer referred to above.

A delay time of the dummy delay circuit DMDL is set to a delay time d1+d2 corresponding to a delay time d1 at the input buffer Rec and a delaytime d2 at an output buffer CLKDRV. Thus, upon clock cycle measurements,the switch is flipped to the dummy delay circuit DMDL so that a delaytime like tCK−(d1+d2) is set by the lattice-like delay circuit SQUAD.After such a delay time has been set, the switch is changed to anotherso that the output signal of the input buffer Rec is outputted throughthe lattice-like delay circuit SQUAD. As a result, the above-describeddelay time tCK−(d1+d2) is set by the lattice-like delay circuit SQUAD.Since the delay time of d1+d2 is produced by the input buffer Rec andthe output driver CLKDRV, an internal clock signal int.CLK delayed justby one clock cycle tCK with respect to a clock signal ext.CLK suppliedfrom an external terminal can be formed.

Since the internal clock signal int.CLK results in a signal delayed bythe delay time of the dummy delay circuit DMDL upon the clock cyclemeasurements in the present embodiment although the circuit can besimplified, it is necessary to add the function of invalidating itsoutput. When it is desired to expand or increase a clock frequencycapable of synchronization, the coarse delay CD1, the edge detector ED1and the multiplexer MPX1 employed in the embodiment shown in FIG. 23 maybe added.

FIG. 37 is a block diagram showing a further embodiment of a clocksynchronous circuit according to the present invention. In the presentembodiment, two lattice-like delay circuits SQUAD for both themeasurement and output are used. Namely, the present embodiment isequivalent to one in which the coarse delays CD1 through CD3 and thelike employed in the embodiment shown in FIG. 23 are omitted. When it isdesired to achieve a reduction in power consumption by the measuringlattice-like delay circuit SQUAD under such a configuration, theabove-described dummy delay circuit DMDL may be intermittently activatedas in the embodiment referred to above.

Operations and effects of the embodiments shown in FIG. 23 and the likeare as follows:

(1) An advantageous effect can be obtained in that a lattice-like delaycircuit is configured wherein a first coarse delay for propagating aclock pulse with relatively low time resolution, a first edge detectorand a first multiplexer are used to form or create a clock signaldelayed by one clock in association with the relatively low timeresolution, a second coarse delay having relatively high timeresolution, a second edge detector and a second multiplexer are used tocorrect an error of the first coarse delay, included in the abovesignal, and a plurality of logic gate means each of which is providedwith impedance means for making coupling between two input signalsinputted between first and second input terminals, said impedance meansbeing provided as a second delay circuit having high time resolution asthe above second coarse delay, and each of which forms or produces anoutput signal obtained by inverting an input signal, are used so as tobe placed in lattice form in first and second signal transferdirections, whereby a high-accuracy and quick-response clock synchronouscircuit can be obtained by using the lattice-like delay circuit whereinthe respective logic gate means extending from the first to the last asseen in the first signal transfer direction are respectivelysuccessively supplied with input clock signals with delays as seen inthe first signal transfer direction, and output signals are obtainedfrom output terminals of the plurality of logic gate means placed in atleast the final stage or the immediately preceding stage as seen in thesecond signal transfer direction and arranged in the first signaltransfer direction

(2) Another advantageous effect can be obtained in that the first coarsedelay comprises three delay circuits corresponding to first Nos. 1, 2and 3, the first multiplexer comprises two multiplexers corresponding tofirst Nos. 1 and 2, and the second coarse delay comprises two delaycircuits corresponding to first Nos. 1 and 2 and they are used for themeasurement of clocks and the formation of output clocks, whereby aclock cycle measuring operation for synchronization can be executedwhile output clock signals are being formed.

(3) A further advantageous effect can be obtained in that in thelattice-like delay circuit that constitutes the second coarse delay, aninput signal supplied to a first input terminal of a logic gate meansplaced in the final stage as seen in the first signal transfer directionand placed in a first stage as seen in the second signal transferdirection is supplied to a second input terminal of a logic gate meansplaced in the first as seen in the first signal transfer direction andplaced in a third stage as seen in the second signal transfer direction,and an output signal of a logic gate means placed in the first as seenin the first and second signal transfer directions is commonly suppliedto first and second input terminals of a logic gate means placed in thefirst as seen in the first signal transfer direction and placed in asecond stage as seen in the second signal transfer direction, wherebythe shortest time as seen in the second signal transfer direction can beequally delayed by the number of stages extending in the first signaltransfer direction, thereby making it possible to achieve small amountsof delay with efficiency

(4) A still further advantageous effect can be obtained in that thefirst Nos. 1 to 3 delay circuits can obtain a desired delay time in asimple configuration by connecting CMOS inverters in tandem and can beset to a low power consumption mode by bringing an input signal to afixed level.

(5) A still further advantageous effect can be obtained in that theinput of the first No. 2 delay circuit is supplied with an input signalthrough a first dummy delay circuit, and an output signal of the firstdummy delay circuit is supplied to the input of the first No. 1 delaycircuit through a second dummy delay circuit for performing timing sothat a delay signal outputted from the second coarse delay is set toreach a predetermined number of stages or later, whereby thelattice-like delay circuit can be activated in a stable operating oractive region.

(6) A still further advantageous effect can be obtained in that thefirst and second edge detectors are provided with latch circuits attheir outputs respectively and are intermittently brought to anoperating state and a non-operating state according to a predeterminedcontrol signal, and they are caused to output detected signals held inthe latch circuits upon the non-operating state, whereby power to beused up by a clock cycle measuring unit can be greatly reduced.

(7) A still further advantageous effect can be obtained in that a clocksignal supplied from an external terminal is inputted through an inputbuffer and a delay circuit having a coarse delay corresponding to anoutput-stage driver and an output signal transmitted through the secondmultiplexer is outputted through the output-stage driver, whereby aninternal clock signal synchronized inclusive of delays of the inputcircuit and driver can be formed.

(8) A still further advantageous effect can be obtained in that owing tothe generation of the above-described predetermined control signal in apredetermined cycle by a timer, power consumption can be greatly reducedwhile clock cycles are being automatically measured with necessary timeintervals.

(9) A still further advantageous effect can be obtained in that a delaysignal formed through a dummy delay circuit for delaying a clock signalsupplied from an external terminal with a delay time corresponding todelay times of an input buffer and the input buffer and output-stagedriver is supplied to a lattice-like delay circuit, delay signals atrespective stages of the lattice-like delay circuit and a one-clockdelayed clock edge of a clock pulse inputted through an input buffer arecompared to detect time coincidence between both edges, after which theresult of detection is held in a latch, and the input of thelattice-like delay circuit is supplied with the output of the inputbuffer to output a clock signal through the output-stage driver, wherebya high-accuracy synchronizing operation corresponding to time resolutionof the lattice-like delay circuit can be performed in a simpleconfiguration.

(10) A still further advantageous effect can be obtained in that a delaysignal formed through a dummy delay circuit for delaying a clock signalsupplied from an external terminal with a delay time corresponding todelay times of an input buffer and the input buffer and output-stagedriver is supplied to a lattice-like delay circuit, delay signals atrespective stages of the lattice-like delay circuit and a one-clockdelayed clock edge of a clock pulse signal inputted through an inputbuffer are compared to detect time coincidence between both edges, theinput of another lattice-like delay circuit identical in configurationto the above is supplied with the output of the input buffer, and amultiplexer is controlled based on the result of detection to take out adelay signal from another lattice-like delay circuit and output a clocksignal through the output-stage driver, whereby a high-accuracy outputclock signal corresponding to the time resolution of the lattice-likedelay circuit can be obtained while a clock cycle measurement and anoutput operation are being performed simultaneously.

(11) A still further advantageous effect can be obtained in that a clocksynchronous circuit using the lattice-like delay circuit described inthe paragraphs (1) through (8) is used in a semiconductor integratedcircuit device provided with a memory array having memory cellsmatrix-placed at points of intersection of a plurality of word lines anda plurality of bit lines and its selection circuit; a clock synchronouscircuit for receiving control and clock signals supplied from externalterminals and generating an internal clock signal corresponding to theclock signal in accordance with each control signal referred to above;and an input/output circuit for outputting a read signal of thecorresponding memory cell in accordance with the synchronized internalclock signal, thereby making it possible to implement on-standby lesspower consumption and high-speed reset while permitting a memoryoperation at a high frequency.

Although the invention, which has been made above by the presentinventors, has been described specifically based on the illustratedembodiments, the invention of the present application is not necessarilylimited to the aforementioned embodiments. It is needless to say thatmany changes can be made to the invention within the scope not departingfrom the substance thereof. Since, for example, a large-scale integratedcircuit provided with clock synchronous circuits every circuit blocksprovides mutual synchronization between internal clock signals everycircuit blocks, an input buffer for receiving therein clock signalssupplied from an external terminal can be omitted. In the embodimentshown in FIG. 1, the same delay circuit may be configured so as to beseparately used in a clock cycle measurement and a clock signal outputoperation on a time basis as in the embodiment shown in FIG. 18. Theclock synchronous circuit according to the present invention can be usedin a microprocessor or various semiconductor integrated circuit deviceswhich constitute peripheral circuits, as well as in a memory such as anSDRAM or the like.

Effects obtained by a typical one of the inventions disclosed in thepresent application will be described in brief as follows: Alattice-like delay circuit is configured wherein a first delay circuitor coarse delay for propagating a clock pulse with relatively low timeresolution, a first edge detector and a first multiplexer are used toform or create a clock signal delayed by one clock in association withthe relatively low time resolution, a second coarse delay havingrelatively high time resolution, a second edge detector and a secondmultiplexer are used to correct an error of the first coarse delay,included in the above signal, and a plurality of logic gate means eachof which is provided with impedance means for making coupling betweentwo input signals inputted between first and second input terminals as asecond delay circuit having high time resolution as the above secondcoarse delay, and each of which produces an output signal obtained byinverting the input signals, are used so as to be placed in lattice formin first and second signal transfer directions. The lattice-like delaycircuit is used wherein the respective logic gate means extending fromthe first to the last as seen in the first signal transfer direction arerespectively successively supplied with input clock signals with theirdelays as seen in the first signal transfer direction, and outputsignals are obtained from output terminals of the plurality of logicgate means placed in at least the final stage or the immediatelypreceding stage as seen in the second signal transfer direction andarranged in the first signal transfer direction. Thus, a high-accuracyand quick-response clock synchronous circuit can be obtained.

We claim:
 1. A clock synchronous circuit comprising: a first delaycircuit which receives therein a first clock signal delayed from areference clock signal and propagates the first clock signal with afirst time resolution; a first edge detector which compares an edge of adelay signal of each stage corresponding to the time resolution of saidfirst delay circuit with a first clock edge of the reference clocksignal to thereby detect time coincidence between both edges; a firstmultiplexer controlled by a signal detected by said first edge detectorso as to output a delay signal which has a timing of a correspondingdelay stage of said first delay circuit; a second delay circuit whichreceives therein a second clock signal obtained through said firstmultiplexer and propagates the second clock signal with a second timeresolution higher in accuracy than the first time resolution; a secondedge detector which compares an edge of a delay signal of each stagecorresponding to the time resolution of said second delay circuit with asecond clock edge of the reference clock signal to thereby detect timecoincidence between both edges; and a second multiplexer controlled by asignal detected by said second edge detector so as to output a delaysignal which has a timing of a corresponding delay stage of said seconddelay circuit; whereby an internal clock signal synchronized with thereference clock signal or a signal corresponding to the reference clocksignal is formed based on a third clock signal obtained through saidsecond multiplexer, said second delay circuit including, a plurality oflogic gate circuits which are respectively provided with impedanceelements for respectively coupling two input signals inputted to firstand second input terminals, said each impedance element being providedbetween the first and second input terminals, and respectively formoutput signals according to the input signals supplied to the first andsecond terminals, said plurality of logic gate circuits being capable ofbeing disposed in lattice form in a first signal transfer direction anda second signal transfer direction, and wherein the first input terminalof a logic gate circuit KL provided as a Kth other than the first asseen in the first signal transfer direction and disposed in an Lth stageas seen in the second signal transfer direction is supplied with asignal outputted from a logic gate circuit provided as the same Kth asseen in the first signal transfer direction and defined as an L−1thstage as seen in the second signal transfer direction or an input clocksignal in the case of the first-stage logic gate circuit, the secondinput terminal of the logic gate circuit KL is supplied with an inputsignal supplied to a first input terminal of a logic gate circuitprovided as the immediately preceding K−1th as seen in the first signaltransfer direction and defined as the same Lth stage as seen in thesecond signal transfer direction; a second input terminal of a logicgate circuit provided as the first as seen in the first signal transferdirection and defined as an Lth as seen in the second signal transferdirection is supplied with an input signal supplied to a first inputterminal of a logic gate circuit defined as the final stage as seen inthe first signal transfer direction, said input signal being in phasewith an input signal supplied to a first input terminal of a logic gatecircuit at a stage preceding the final stage as seen in the secondsignal transfer direction; the first and second input terminals of thelogic gate circuits defined as the first stage as seen in the secondsignal transfer direction and provided as the first as seen in the firstsignal transfer direction are respectively supplied with a clock signalcorresponding to the second clock signal, and the input clock signalssupplied to the first input terminals of the respective logic gatecircuits extending from the second to the last as seen in the firstsignal transfer are delayed in order in the first signal transferdirection; and output signals are respectively obtained from outputterminals of a plurality of logic gate circuits placed in at least aplural-numbered stage as seen in the second signal transfer directionand arranged in the first signal transfer direction.
 2. A clocksynchronous circuit according to claim 1, further comprising, third andfourth delay circuits similar in circuit configuration to said firstdelay circuit; a third multiplexer provided in association with saidfourth delay circuit; and a fifth delay circuit similar in circuitconfiguration to said second delay circuit, and wherein said firstmultiplexer selects a delay signal of each stage of said third delaycircuit in accordance with the detected signal of said first edgedetector, said third multiplexer selects a delay signal of each stage ofsaid fourth delay circuit in accordance with the detected signal of saidfirst edge detector, said second delay circuit has an input which issupplied with the output signal of said first multiplexer to form adelay signal supplied to said second edge detector, and said secondmultiplexer selects a delay signal of each stage of said fifth delaycircuit in accordance with the detected signal of said second edgedetector.
 3. A clock synchronous circuit according to claim 1 or 2,wherein a delay circuit, which constitutes said second delay circuit, isconstructed so that an input signal supplied to a first input terminalof a logic gate circuit placed in the final stage as seen in the firstsignal transfer direction and placed in a first stage as seen in thesecond signal transfer direction is supplied to a second input terminalof a logic gate circuit placed in the first as seen in the first signaltransfer direction and placed in a third stage as seen in the secondsignal transfer direction, and an output signal of a logic gate circuitplaced in the first as seen in the first and second signal transferdirections is commonly supplied to first and second input terminals of alogic gate circuit placed in the first as seen in the first signaltransfer direction and placed in a second stage as seen in the secondsignal transfer direction.
 4. A clock synchronous circuit according toclaim 2, wherein said third and fourth delay circuits comprise CMOSinverter circuits connected in tandem respectively.
 5. A clocksynchronous circuit according to claim 2, wherein the input of saidthird delay circuit is supplied with an input signal through a firstdummy delay circuit, and an output signal of the first dummy delaycircuit is supplied to the input of said first delay circuit through asecond dummy delay circuit for performing timing so that a delay signaloutputted from said second delay circuit is set to reach a predeterminednumber of stages or later.
 6. A clock synchronous circuit according toclaim 2, wherein said first and second edge detectors include latchcircuits provided at their outputs respectively and are intermittentlybrought to an operating state according to a predetermined controlsignal, and said first and second edge detectors respectively outputdetected signals held in the latch circuits upon a non-operating state.7. A clock synchronous circuit according to claim 1 or 2 wherein thereference clock signal is inputted through an input buffer for receivingan external clock signal supplied from an external terminal, and anoutput signal transmitted through said second multiplexer is outputtedthrough an output-stage driver, and the external clock signal and theoutput signal of the output-stage driver are synchronized with eachother.
 8. A clock synchronous circuit according to claim 7, wherein saidpredetermined control signal is generated in a predetermined cycle by atimer.
 9. A clock synchronous circuit comprising: an input buffer whichreceives a clock signal supplied from an external terminal; a firstdelay circuit which delays the clock signal transmitted through saidinput buffer with a delay time corresponding to delay time intervals ofsaid input buffer and an output-stage driver; a switch circuit whichselectively transfers an output signal of said first delay circuit or anoutput signal of said input buffer; a second delay circuit which delaysa signal inputted through said switch circuit; and a selection circuithaving a latch function of comparing delay signals at respective stagesof said second delay circuit with a one-clock delayed clock edge of aclock signal inputted through said input buffer to thereby detect timecoincidence between both edges and holding the result of detection andfor outputting the delay signals at the respective stages according tothe result of detection, and wherein said switch circuit is connected tosaid first delay circuit side so that a detected signal is formed bysaid selection circuit, said switch circuit is switched to said inputbuffer side to output each delay signal of said second delay circuitthrough said output-stage driver according to the result of detectionheld in said latch function, and said second delay circuit including, aplurality of logic gate circuits which are respectively provided withimpedance elements for respectively coupling two input signals inputtedto first and second input terminals, said each impedance element beingprovided between the first and second input terminals, and respectivelyform output signals according to the input signals supplied to the firstand second terminals, said plurality of logic gate circuits beingcapable of being disposed in lattice form in a first signal transferdirection and a second signal transfer direction, and wherein the firstinput terminal of a logic gate circuit KL provided as a Kth other thanthe first as seen in the first signal transfer direction and disposed inan Lth stage as seen in the second signal transfer direction is suppliedwith a signal outputted from a logic gate circuit provided as the sameKth as seen in the first signal transfer direction and defined as anL−1th stage as seen in the second signal transfer direction or an inputclock signal in the case of the first-stage logic gate circuit, thesecond input terminal of the logic gate circuit KL is supplied with aninput signal supplied to a first input terminal of a logic gate circuitprovided as the immediately preceding K−1th as seen in the first signaltransfer direction and defined as the same Lth stage as seen in thesecond signal transfer direction; a second input terminal of a logicgate circuit provided as the first as seen in the first signal transferdirection and defined as an Lth as seen in the second signal transferdirection is supplied with an input signal supplied to a first inputterminal of a logic gate circuit defined as the final stage as seen inthe first signal transfer direction, said input signal being in phasewith an input signal supplied to a first input terminal of a logic gatecircuit at a stage preceding the final stage as seen in the secondsignal transfer direction; the first and second input terminals of thelogic gate circuits defined as the first stage as seen in the secondsignal transfer direction and provided as the first as seen in the firstsignal transfer direction are respectively supplied with a clock signalcorresponding to the input signal outputted through said switch circuit,and the input clock signals supplied to the first input terminals of therespective logic gate circuits extending from the second to the last asseen in the first signal transfer direction are delayed in order in thefirst signal transfer direction; and output signals are respectivelyobtained from output terminals of a plurality of logic gate circuitsplaced in at least a plural-numbered stage as seen in the second signaltransfer direction and arranged in the first signal transfer direction.10. A clock synchronous circuit comprising: an input buffer whichreceives a clock signal supplied from an external terminal; a firstdelay circuit which delays the clock signal transmitted through saidinput buffer with a delay time corresponding to delay time intervals ofsaid input buffer and an output-stage driver; a second delay circuitwhich receives an output signal of said first delay circuit therein anddelaying the output signal; an edge detector which compares delaysignals at respective stages of said second delay circuit with aone-clock delayed clock edge of a clock signal inputted through saidinput buffer to thereby detect time coincidence between both edges; anda third delay circuit which receives therein the clock signal inputtedthrough said input buffer and delay the clock signal, whereby the delaysignal of said third delay circuit is outputted through saidoutput-stage driver according to the result of detection by said edgedetector, said second and third delay circuits each including, aplurality of logic gate circuits which are respectively provided withimpedance elements for respectively coupling two input signals inputtedto first and second input terminals, said each impedance element beingprovided between the first and second input terminals, and respectivelyform output signals according to the input signals supplied to the firstand second terminals, said plurality of logic gate circuits beingcapable of being disposed in lattice form in a first signal transferdirection and a second signal transfer direction, and wherein the firstinput terminal of a logic gate circuit KL provided as a Kth other thanthe first as seen in the first signal transfer direction and disposed inan Lth stage as seen in the second signal transfer direction is suppliedwith a signal outputted from a logic gate circuit provided as the sameKth as seen in the first signal transfer direction and defined as anL−1th stage as seen in the second signal transfer direction or an inputclock signal in the case of the first-stage logic gate circuit, thesecond input terminal of the logic gate circuit KL is supplied with aninput signal supplied to a first input terminal of a logic gate circuitprovided as the immediately preceding K−1th as seen in the first signaltransfer direction and defined as the same Lth stage as seen in thesecond signal transfer direction; a second input terminal of a logicgate circuit provided as the first as seen in the first signal transferdirection and defined as an Lth as seen in the second signal transferdirection is supplied with an input signal supplied to a first inputterminal of a logic gate circuit defined as the final stage as seen inthe first signal transfer direction, said input signal being in phasewith an input signal supplied to a first input terminal of a logic gatecircuit at a stage preceding the final stage as seen in the secondsignal transfer direction; clock signals supplied to first inputterminals of respective logic gate circuits defined as a first stage asseen in the second signal transfer direction and extending from thefirst to the last as seen in the first signal transfer direction aredelayed in order in the first signal transfer direction; and outputsignals are respectively obtained from output terminals of a pluralityof logic gate circuits placed in at least a plural-numbered stage asseen in the second signal transfer direction and arranged in the firstsignal transfer direction.
 11. A semiconductor integrated circuit devicecomprising: a memory array in which memory cells are placed in matrixform at points of intersection of a plurality of word lines and aplurality of bit lines; an address selection circuit which selects acorresponding memory cell in said memory array; a clock synchronouscircuit which generates an internal clock signal corresponding to anexternal clock signal supplied from an external terminal; and an outputcircuit which outputs a read signal of said memory cell in accordancewith the internal clock signal generated by said clock synchronouscircuit, said clock synchronous circuit including a first delay circuitwhich receives therein a first clock signal delayed from a referenceclock signal corresponding to the external clock signal and propagatesthe first clock signal with a first time resolution; a first edgedetector which compares an edge of a delay signal of each stagecorresponding to the time resolution of said first delay circuit with afirst clock edge of the reference clock signal to thereby detect timecoincidence between both edges; a first multiplexer controlled by asignal detected by said first edge detector so as to output a delaysignal which has a timing of a corresponding delay stage of said firstdelay circuit; a second delay circuit which receives therein a secondclock signal obtained through said first multiplexer and propagates thesecond clock signal with a second time resolution higher in accuracythan the first time resolution; a second edge detector which compares anedge of a delay signal of each stage corresponding to the timeresolution of said second delay circuit with a second clock edge of thereference clock signal to thereby detect time coincidence between bothedges; and a second multiplexer controlled by a signal detected by saidsecond edge detector so as to output a delay signal which has a timingof a corresponding delay stage of said second delay circuit; whereby theinternal clock signal synchronized with the external clock signal isformed based on a third clock signal obtained through said secondmultiplexer, said second delay circuit including, a plurality of logicgate circuits which are respectively provided with impedance elementsfor respectively coupling two input signals inputted to first and secondinput terminals, said each impedance element being provided between thefirst and second input terminals, and respectively form output signalsaccording to the input signals supplied to the first and secondterminals, said plurality of logic gate circuits being capable of beingdisposed in lattice form in a first signal transfer direction and asecond signal transfer direction, and wherein the first input terminalof a logic gate circuit KL provided as a Kth other than the first asseen in the first signal transfer direction and disposed in an Lth stageas seen in the second signal transfer direction is supplied with asignal outputted from a logic gate circuit provided as the same Kth asseen in the first signal transfer direction and defined as an L−1thstage as seen in the second signal transfer direction or an input clocksignal in the case of the first-stage logic gate circuit, the secondinput terminal of the logic gate circuit KL is supplied with an inputsignal supplied to a first input terminal of a logic gate circuitprovided as the immediately preceding K−1th as seen in the first signaltransfer direction and defined as the same Lth stage as seen in thesecond signal transfer direction; a second input terminal of a logicgate circuit provided as the first as seen in the first signal transferdirection and defined as an Lth as seen in the second signal transferdirection is supplied with an input signal supplied to a first inputterminal of a logic gate circuit defined as the final stage as seen inthe first signal transfer direction, said input signal being in phasewith an input signal supplied to a first input terminal of a logic gatecircuit at a stage preceding the final stage as seen in the secondsignal transfer direction; the input clock signals supplied to the firstinput terminals of the respective logic gate circuits placed in a firststage as seen in the second signal transfer direction and extending fromthe first to the last as seen in the first signal transfer direction aredelayed in order in the first signal transfer direction; and outputsignals are respectively obtained from output terminals of a pluralityof logic gate circuits placed in at least a plural-numbered stage asseen in the second signal transfer direction and arranged in the firstsignal transfer direction.
 12. A semiconductor integrated circuit deviceaccording to claim 11, further comprising, third and fourth delaycircuits similar in circuit configuration to said first delay circuit; athird multiplexer provided so as to correspond to said third delaycircuit; and a fifth delay circuit similar in circuit configuration tosaid second delay circuit, and wherein said first multiplexer selects adelay signal of each stage of said third delay circuit in accordancewith the detected signal of said first edge detector, said thirdmultiplexer selects a delay signal of each stage of said fourth delaycircuit in accordance with the detected signal of said first edgedetector, said second delay circuit has an input which is supplied withthe output signal of said first multiplexer to form a delay signalsupplied to said second edge detector, and said second multiplexerselects a delay signal of each stage of said fifth delay circuit inaccordance with the detected signal of said second edge detector.
 13. Asemiconductor integrated circuit device according to claim 12, whereinthe input of said third delay circuit is supplied with an input signalthrough a first dummy delay circuit, and an output signal of said firstdummy delay circuit is supplied to the input of said first delay circuitthrough a second dummy delay circuit which performs timing so that adelay signal outputted from said second delay circuit is set to reach apredetermined number of stages or later.
 14. A semiconductor integratedcircuit device according to claim 13, wherein the reference clock signalis inputted through an input buffer for receiving an external clocksignal supplied from an external terminal, said first dummy delaycircuit is brought to an operating state or a non-operating stateaccording to a clock enable signal and fixes an output signal to eitherone of levels upon the non-operating state, and said first and secondedge detectors are provided with latch circuits at their outputs andhold detected results therein, respectively.
 15. A semiconductorintegrated circuit device according to claim 13 or 14, wherein saidfirst dummy delay circuit and said first and second edge detectors arerespectively intermittently brought to an operating state according to acontrol signal generated in a predetermined cycle by a timerincorporated in said semiconductor integrated circuit device.
 16. Asemiconductor integrated circuit device according to claim 10 or 11,wherein the input of data from or output data to the outside isperformed according to both the leading and trailing edges of theinternal clock signal produced by said clock synchronous circuit.